Lines Matching defs:TII
69 const TargetInstrInfo &TII = *STI.getInstrInfo();
75 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
88 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
94 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
127 bool CanChangeCC, const TargetInstrInfo &TII,
136 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), DestReg)
162 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
167 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
171 BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)
177 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm ), LdReg)
211 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MRS_M), CPSRSaveReg)
216 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi32imm), LdReg)
220 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MSR_M))
226 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi32imm), LdReg)
237 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
255 const TargetInstrInfo &TII,
368 TII, MRI, MIFlags);
377 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
394 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
427 const ARMBaseInstrInfo &TII) const {
443 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
472 BuildMI(MBB, II, dl, TII.get(ARM::tMOVr), DestReg)
484 MI.setDesc(TII.get(NewOpc));
528 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
536 bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
553 const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
587 if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
609 Offset, false, TII, *this);
617 BuildMI(MBB, II, dl, TII.get(ARM::tADDhirr), TmpReg)
624 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
628 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
645 Offset, false, TII, *this);
653 BuildMI(MBB, II, dl, TII.get(ARM::tADDhirr), VReg)
660 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
662 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));