Lines Matching +full:0 +full:xc000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
239 case ARM_AM::da: return 0;
251 case ARM_AM::lsl: return 0;
311 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
326 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
327 return 0;
345 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
346 return 0;
350 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
477 unsigned Bit24 = EncodedValue & 0x01000000;
479 EncodedValue &= 0xEFFFFFFF;
481 EncodedValue |= 0x0F000000;
494 EncodedValue &= 0xF0FFFFFF;
495 EncodedValue |= 0x09000000;
508 EncodedValue &= 0x00FFFFFF;
509 EncodedValue |= 0xEE000000;
521 EncodedValue |= 0xC000000; // Set bits 27-26
533 EncodedValue &= 0x0FFFFFFF;
534 EncodedValue |= 0xE0000000;
592 // Special value for #-0
594 SImm = 0;
599 if (SImm < 0) {
621 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
624 return 0;
631 uint32_t S = (offset & 0x800000) >> 23;
632 uint32_t J1 = (offset & 0x400000) >> 22;
633 uint32_t J2 = (offset & 0x200000) >> 21;
634 J1 = (~J1 & 0x1);
635 J2 = (~J2 & 0x1);
639 offset &= ~0x600000;
710 for (int i = 0; i < NumOp-1; ++i) {
714 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
786 unsigned Val = 0;
794 bool I = (Val & 0x800000);
795 bool J1 = (Val & 0x400000);
796 bool J2 = (Val & 0x200000);
798 Val &= ~0x400000;
800 Val |= 0x400000;
803 Val &= ~0x200000;
805 Val |= 0x200000;
821 uint32_t Val = 0x2000;
825 Val = 0x1000;
826 SoImmVal = 0;
827 } else if (offset < 0) {
828 Val = 0x1000;
832 Val = 0x2000;
839 Val = 0x1000;
863 Val = 0x1000;
864 else if (Val < 0) {
866 Val |= 0x1000;
886 assert(OpIdx > 0 && "IT mask appears first!");
891 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
919 // {2-0} = Rn
933 // {4-0} = szimm5
968 // {12} = (U)nsigned (add == '1', sub == '0')
969 // {11-0} = imm12
970 unsigned Reg = 0, Imm12 = 0;
984 Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
994 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
1001 Offset = 0;
1003 } else if (Offset < 0) {
1009 uint32_t Binary = Imm12 & 0xfff;
1027 // for #-0.
1029 // {Bits} = (U)nsigned (add == '1', sub == '0')
1030 // {(Bits-1)-0} = immediate
1032 bool isAdd = Imm >= 0;
1035 if (Imm < 0)
1054 // {2-0} Qm
1074 // {7-0} Imm
1081 bool isAdd = Imm >= 0;
1088 Imm &= 0x7f;
1091 Imm |= 0x80;
1105 // {8} = (U)nsigned (add == '1', sub == '0')
1106 // {7-0} = imm8
1113 Imm8 = 0;
1119 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1130 // for #-0.
1131 assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!");
1132 uint32_t Binary = (Imm8 >> 2) & 0xff;
1147 // {7} = (A)dd (add == '1', sub == '0')
1148 // {6-0} = imm7
1158 // for #-0.
1159 uint32_t Binary = (Imm7 >> 2) & 0xff;
1174 // {7-0} = imm8
1186 // {11-0} = imm{11-0}
1207 return (int32_t(Value) & 0xffff0000) >> 16;
1209 return (int32_t(Value) & 0x0000ffff);
1212 return (int32_t(Value) & 0xff000000) >> 24;
1214 return (int32_t(Value) & 0x00ff0000) >> 16;
1216 return (int32_t(Value) & 0x0000ff00) >> 8;
1218 return (int32_t(Value) & 0x000000ff);
1256 Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1257 return 0;
1283 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1285 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1289 // {11-0} = shifter
1290 // {3-0} = Rm
1291 // {4} = 0
1307 // {13} 1 == imm12, 0 == Rm
1309 // {11-0} imm12/Rm
1314 bool isReg = MO.getReg() != 0;
1321 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1331 // {3-0} Rm
1334 bool isAdd = MO1.getImm() != 0;
1342 // {9} 1 == imm8, 0 == Rm
1345 // {3-0} imm3_0/Rm
1350 bool isImm = MO.getReg() == 0;
1362 // {13} 1 == imm8, 0 == Rm
1366 // {3-0} imm3_0/Rm
1378 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1386 bool isImm = MO1.getReg() == 0;
1400 // {7-0} = imm8
1407 return MO1.getImm() & 0xff;
1417 // {2-0} = Rn
1422 return ((Imm5 & 0x1f) << 3) | Rn;
1442 // {8} = (U)nsigned (add == '1', sub == '0')
1443 // {7-0} = imm8
1450 Imm8 = 0;
1460 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1482 // {8} = (U)nsigned (add == '1', sub == '0')
1483 // {7-0} = imm8
1490 Imm8 = 0;
1500 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1524 // {3-0} = Rm.
1528 // {7} = 0
1539 unsigned SBits = 0;
1549 case ARM_AM::lsl: SBits = 0x1; break;
1550 case ARM_AM::lsr: SBits = 0x3; break;
1551 case ARM_AM::asr: SBits = 0x5; break;
1552 case ARM_AM::ror: SBits = 0x7; break;
1560 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1571 // {3-0} = Rm.
1572 // {4} = 0
1584 unsigned SBits = 0;
1594 case ARM_AM::lsl: SBits = 0x0; break;
1595 case ARM_AM::lsr: SBits = 0x2; break;
1596 case ARM_AM::asr: SBits = 0x4; break;
1597 case ARM_AM::ror: SBits = 0x6; break;
1599 Binary |= 0x60;
1606 assert(Offset < 32 && "Offset must be in range 0-31!");
1646 tmp = 0;
1647 } else if (tmp < 0) {
1663 unsigned Value = 0;
1665 if (static_cast<int32_t>(tmp) < 0)
1680 // {3-0} = Rm.
1681 // {4} = 0
1693 unsigned SBits = 0;
1701 case ARM_AM::lsl: SBits = 0x0; break;
1702 case ARM_AM::lsr: SBits = 0x2; break;
1703 case ARM_AM::asr: SBits = 0x4; break;
1705 case ARM_AM::ror: SBits = 0x6; break;
1726 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1736 // {7-0} = Number of registers
1739 // {15-0} = Bitfield of GPRs.
1744 unsigned Binary = 0;
1749 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1750 Binary |= (RegNo & 0x1f) << 8;
1785 unsigned Align = 0;
1791 case 8: Align = 0x01; break;
1792 case 16: Align = 0x02; break;
1793 case 32: Align = 0x03; break;
1809 unsigned Align = 0;
1815 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1816 case 2: Align = 0x00; break;
1817 case 4: Align = 0x03; break;
1836 unsigned Align = 0;
1842 case 8: Align = 0x01; break;
1843 case 16: Align = 0x03; break;
1854 if (MO.getReg() == 0) return 0x0D;
1911 support::endian::write<uint16_t>(CB, Binary & 0xffff, Endian);
1934 const MCOperand BranchMO = MI.getOperand(0);
1941 Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1942 return 0;
1959 int Imm = 0;
1963 unsigned PrevBit = 0;
1964 for (int i = 3; i >= 0; --i) {
1968 if ((Value & ~(~0U << i)) == 0) {
1992 assert(0 && "Unexpected Condition!");
1993 return 0;
1996 return 0;