Lines Matching full:b1
300 def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "u", 0b1>;
301 def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "u", 0b1>;
302 def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v2i1, 0b10, "u", 0b1>;
303 def MVE_v2u64 : MVEVectorVTInfo<v2i64, ?, v2i1, ?, 0b11, "u", 0b1>;
312 def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b11, "p", 0b1>;
446 let Inst{8} = 0b1;
562 "$RdaLo, $RdaHi, $sat, $Rm", op5, 0b1, pattern> {
568 def MVE_ASRLr : MVE_ScalarShiftDRegReg<"asrl", 0b1, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
584 def MVE_SQRSHRL : MVE_ScalarShiftDRegRegWithSat<"sqrshrl", 0b1>;
585 def MVE_SQSHLL : MVE_ScalarShiftDRegImm<"sqshll", 0b11, 0b1>;
586 def MVE_SRSHRL : MVE_ScalarShiftDRegImm<"srshrl", 0b10, 0b1>;
589 def MVE_UQSHLL : MVE_ScalarShiftDRegImm<"uqshll", 0b00, 0b1>;
590 def MVE_URSHRL : MVE_ScalarShiftDRegImm<"urshrl", 0b01, 0b1>;
621 let Inst{8} = 0b1;
626 let Inst{0} = 0b1;
692 0b1, VTI.Unsigned, VTI.Size>;
798 0b1, VTI.Unsigned>;
843 let Inst{8} = 0b1;
904 let Inst{8} = 0b1;
1052 sz, bit_28, 0b1, X, bit_8, bit_0, VTI.Size>;
1103 0b1, bit_8, bit_0>;
1111 sz, 0b1, 0b0, bit_8, 0b0>;
1116 sz, bit_28, 0b0, 0b1>;
1119 defm MVE_VMLADAV : MVE_VMLADAV_multi<MVE_v16s8, MVE_v16u8, 0b0, 0b1>;
1121 defm MVE_VMLADAV : MVE_VMLADAV_multi<MVE_v4s32, MVE_v4u32, 0b1, 0b0>;
1123 defm MVE_VMLSDAV : MVE_VMLSDAV_multi<MVE_v16s8, 0b0, 0b1>;
1125 defm MVE_VMLSDAV : MVE_VMLSDAV_multi<MVE_v4s32, 0b1, 0b0>;
1292 sz, bit_28, 0b1, X, bit_8, bit_0, vecsize, pattern>;
1301 bit_28, 0b1, bit_8, bit_0, vecsize, pattern>;
1306 0b0, 0b0, 0b1, 0b0, VTI.Size, pattern>;
1308 0b0, 0b1, 0b0, 0b1, 0b0, VTI.Size, pattern>;
1335 VTI.Size{1}, 0b1, 0b0, 0b0, 0b0, VTI.Size, pattern>;
1393 defm "" : MVE_VMLALDAVBase_AX<iname, suffix, sz, bit_28, 0b0, 0b1, vecsize, pattern>;
1397 defm MVE_VMLSLDAV : MVE_VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0, 0b10>;
1398 defm MVE_VRMLSLDAVH : MVE_VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1, 0b10>;
1428 let Inst{28} = 0b1;
1433 let Inst{11} = 0b1;
1434 let Inst{8} = 0b1;
1435 let Inst{6} = 0b1;
1436 let Inst{4} = 0b1;
1452 defm MVE_VMINNMf32 : MVE_VMINMAXNM_m<"vminnm", 0b1, MVE_v4f32, fminnum, int_arm_mve_min_predicated>;
1453 defm MVE_VMINNMf16 : MVE_VMINMAXNM_m<"vminnm", 0b1, MVE_v8f16, fminnum, int_arm_mve_min_predicated>;
1466 let Inst{6} = 0b1;
1483 : MVE_VMINMAX_m<"vmin", 0b1, VTI, !if(VTI.Unsigned, umin, smin), int_arm_mve_min_predicated>;
1526 let Inst{6} = 0b1;
1527 let Inst{4} = 0b1;
1537 let Inst{28} = 0b1;
1544 let Inst{6} = 0b1;
1592 let Inst{28} = 0b1;
1624 let Inst{6} = 0b1;
1625 let Inst{4} = 0b1;
1630 def MVE_VEOR : MVE_bit_ops<"veor", 0b00, 0b1>;
1701 let Inst{8} = 0b1;
1703 let Inst{4} = 0b1;
1761 let bit_20 = 0b1;
1810 let Inst{5} = 0b1;
1821 let Inst{22} = 0b1;
1832 def MVE_VMOV_from_lane_u16 : MVE_VMOV_lane_16<"u16", 0b1, MVE_VMOV_from_lane>;
1834 def MVE_VMOV_from_lane_u8 : MVE_VMOV_lane_8 < "u8", 0b1, MVE_VMOV_from_lane>;
1954 let Inst{6} = 0b1;
1967 let Inst{4} = 0b1;
2028 defm MVE_VQRDMULHi8 : MVE_VQxDMULH<"vqrdmulh", MVE_v16s8, 0b1>;
2029 defm MVE_VQRDMULHi16 : MVE_VQxDMULH<"vqrdmulh", MVE_v8s16, 0b1>;
2030 defm MVE_VQRDMULHi32 : MVE_VQxDMULH<"vqrdmulh", MVE_v4s32, 0b1>;
2058 : MVE_VADDSUB_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>;
2078 let Inst{4} = 0b1;
2086 : MVE_VQADDSUB<"vqsub", suffix, U, 0b1, size>;
2303 : MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
2396 def MVE_VDUP16 : MVE_VDUP<"16", 0b0, 0b1, 0b01>;
2397 def MVE_VDUP8 : MVE_VDUP<"8", 0b1, 0b0, 0b00>;
2459 let Inst{28} = 0b1;
2465 let Inst{6} = 0b1;
2500 let Inst{28} = 0b1;
2509 let Inst{6} = 0b1;
2605 let Inst{4} = 0b1;
2621 def MVE_VMOVimmi64 : MVE_mod_imm<"vmov", "i64", {1,1,1,0}, 0b1, (ins nImmSplatI64:$imm), 0b11>;
2625 def MVE_VMVNimmi16 : MVE_mod_imm<"vmvn", "i16", {1,0,?,0}, 0b1, (ins nImmSplatI16:$imm), 0b01> {
2628 def MVE_VMVNimmi32 : MVE_mod_imm<"vmvn", "i32", {?,?,?,?}, 0b1, (ins nImmVMOVI32:$imm), 0b10> {
2681 let Inst{0} = 0b1;
2704 : MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>;
2732 let Inst{21} = 0b1;
2759 let Inst{21} = 0b1;
2827 let Inst{21} = 0b1;
2855 let Inst{20} = 0b1;
2860 def MVE_VSHLL_imms8th : MVE_VSHLL_imm8 <"vshllt", "s8", 0b0, 0b1>;
2861 def MVE_VSHLL_immu8bh : MVE_VSHLL_imm8 <"vshllb", "u8", 0b1, 0b0>;
2862 def MVE_VSHLL_immu8th : MVE_VSHLL_imm8 <"vshllt", "u8", 0b1, 0b1>;
2864 def MVE_VSHLL_imms16th : MVE_VSHLL_imm16<"vshllt", "s16", 0b0, 0b1>;
2865 def MVE_VSHLL_immu16bh : MVE_VSHLL_imm16<"vshllb", "u16", 0b1, 0b0>;
2866 def MVE_VSHLL_immu16th : MVE_VSHLL_imm16<"vshllt", "u16", 0b1, 0b1>;
2879 let Inst{0} = 0b1;
2889 let Inst{12} = 0b1;
2895 defm MVE_VSHLL_lwu8 : MVE_VSHLL_lw<"vshll", "u8", 0b00, 0b1, "$Qd, $Qm, #8">;
2896 defm MVE_VSHLL_lwu16 : MVE_VSHLL_lw<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
2951 let Inst{0} = 0b1;
2956 def MVE_VRSHRNi16bh : MVE_VxSHRN<"vrshrnb", "i16", 0b0, 0b1, shr_imm8, 0b01> {
2959 def MVE_VRSHRNi16th : MVE_VxSHRN<"vrshrnt", "i16", 0b1, 0b1, shr_imm8, 0b01> {
2962 def MVE_VRSHRNi32bh : MVE_VxSHRN<"vrshrnb", "i32", 0b0, 0b1, shr_imm16, 0b10> {
2963 let Inst{20} = 0b1;
2965 def MVE_VRSHRNi32th : MVE_VxSHRN<"vrshrnt", "i32", 0b1, 0b1, shr_imm16, 0b10> {
2966 let Inst{20} = 0b1;
2972 def MVE_VSHRNi16th : MVE_VxSHRN<"vshrnt", "i16", 0b1, 0b0, shr_imm8, 0b01> {
2976 let Inst{20} = 0b1;
2978 def MVE_VSHRNi32th : MVE_VxSHRN<"vshrnt", "i32", 0b1, 0b0, shr_imm16, 0b10> {
2979 let Inst{20} = 0b1;
3000 "vqrshrunb", "s16", 0b1, 0b0, shr_imm8, 0b01> {
3004 "vqrshrunt", "s16", 0b1, 0b1, shr_imm8, 0b01> {
3008 "vqrshrunb", "s32", 0b1, 0b0, shr_imm16, 0b10> {
3009 let Inst{20} = 0b1;
3012 "vqrshrunt", "s32", 0b1, 0b1, shr_imm16, 0b10> {
3013 let Inst{20} = 0b1;
3021 "vqshrunt", "s16", 0b0, 0b1, shr_imm8, 0b01> {
3026 let Inst{20} = 0b1;
3029 "vqshrunt", "s32", 0b0, 0b1, shr_imm16, 0b10> {
3030 let Inst{20} = 0b1;
3055 let Inst{28} = 0b1;
3060 let Inst{20} = 0b1;
3063 let Inst{28} = 0b1;
3064 let Inst{20} = 0b1;
3068 defm MVE_VQRSHRNbh : MVE_VxQRSHRN_types<"vqrshrnb", 0b1, 0b0>;
3069 defm MVE_VQRSHRNth : MVE_VxQRSHRN_types<"vqrshrnt", 0b1, 0b1>;
3071 defm MVE_VQSHRNth : MVE_VxQRSHRN_types<"vqshrnt", 0b0, 0b1>;
3154 let Inst{6} = 0b1;
3190 defm MVE_VQSHL_by_vec : mve_shift_by_vec_multi<"vqshl", 0b1, 0b0>;
3191 defm MVE_VQRSHL_by_vec : mve_shift_by_vec_multi<"vqrshl", 0b1, 0b1>;
3192 defm MVE_VRSHL_by_vec : mve_shift_by_vec_multi<"vrshl", 0b0, 0b1>;
3216 let Inst{23} = 0b1;
3222 let Inst{4} = 0b1;
3240 let Inst{28} = 0b1;
3259 let Inst{21} = 0b1;
3262 def MVE_VSLIimm8 : MVE_VSxI_imm<"vsli", "8", 0b1, imm0_7, 0b00> {
3266 def MVE_VSLIimm16 : MVE_VSxI_imm<"vsli", "16", 0b1, imm0_15, 0b01> {
3270 def MVE_VSLIimm32 : MVE_VSxI_imm<"vsli", "32", 0b1,imm0_31, 0b10> {
3271 let Inst{21} = 0b1;
3329 let Inst{21} = 0b1;
3332 let Inst{21} = 0b1;
3342 let Inst{28} = 0b1;
3362 let Inst{21} = 0b1;
3401 let Inst{21} = 0b1;
3405 let Inst{21} = 0b1;
3460 let Inst{28} = 0b1;
3470 let Inst{28} = 0b1;
3476 let Inst{21} = 0b1;
3480 let Inst{28} = 0b1;
3481 let Inst{21} = 0b1;
3505 let Inst{21} = 0b1;
3553 let Inst{6} = 0b1;
3565 let Inst{28} = 0b1;
3622 let Inst{28} = 0b1;
3630 let Inst{4} = 0b1;
3661 let Inst{28} = 0b1;
3665 let Inst{21} = 0b1;
3729 def "" : MVE_VADDSUBFMA_fp<iname, VTI.Suffix, VTI.Size, 0b1, 0b0, fms,
3802 let Inst{28} = 0b1;
3805 let Inst{23} = 0b1;
3845 let Inst{28} = 0b1;
3848 let Inst{21} = 0b1;
3901 let Inst{21} = 0b1;
3908 let Inst{4} = 0b1;
3928 : MVE_VCVT_fix<suffix, 0b1, U, op, MVE_VCVT_imm<32>> {
3933 let Inst{20} = 0b1;
3966 defm MVE_VCVTs16f16_fix : MVE_VCVT_fix_f16_m<0b0, 0b1, MVE_v8s16, MVE_v8f16>;
3967 defm MVE_VCVTf16u16_fix : MVE_VCVT_fix_f16_m<0b1, 0b0, MVE_v8f16, MVE_v8u16>;
3968 defm MVE_VCVTu16f16_fix : MVE_VCVT_fix_f16_m<0b1, 0b1, MVE_v8u16, MVE_v8f16>;
3970 defm MVE_VCVTs32f32_fix : MVE_VCVT_fix_f32_m<0b0, 0b1, MVE_v4s32, MVE_v4f32>;
3971 defm MVE_VCVTf32u32_fix : MVE_VCVT_fix_f32_m<0b1, 0b0, MVE_v4f32, MVE_v4u32>;
3972 defm MVE_VCVTu32f32_fix : MVE_VCVT_fix_f32_m<0b1, 0b1, MVE_v4u32, MVE_v4f32>;
3980 let Inst{28} = 0b1;
4037 let Inst{28} = 0b1;
4100 let Inst{28} = 0b1;
4154 let Inst{0} = 0b1;
4189 defm MVE_VMINNMAf32 : MVE_VMINNMA<MVE_v4f32, 0b1>;
4190 defm MVE_VMINNMAf16 : MVE_VMINNMA<MVE_v8f16, 0b1>;
4239 : MVE_VCMPqq<suffix, 0b1, size, pred_basic_i, size> {
4245 : MVE_VCMPqq<suffix, 0b1, size, pred_basic_u, size> {
4247 let Inst{0} = 0b1;
4251 : MVE_VCMPqq<suffix, 0b1, size, pred_basic_s, size> {
4252 let Inst{12} = 0b1;
4256 def MVE_VCMPf16 : MVE_VCMPqqf<"f16", 0b1>;
4287 let Inst{6} = 0b1;
4304 : MVE_VCMPqr<suffix, 0b1, size, pred_basic_i, size> {
4310 : MVE_VCMPqr<suffix, 0b1, size, pred_basic_u, size> {
4312 let Inst{5} = 0b1;
4316 : MVE_VCMPqr<suffix, 0b1, size, pred_basic_s, size> {
4317 let Inst{12} = 0b1;
4321 def MVE_VCMPf16r : MVE_VCMPqrf<"f16", 0b1>;
4592 defm MVE_VQDMLADHX : MVE_VQxDMLxDH_multi<"vqdmladhx", 0b1, 0b0, 0b0>;
4593 defm MVE_VQRDMLADH : MVE_VQxDMLxDH_multi<"vqrdmladh", 0b0, 0b1, 0b0>;
4594 defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
4595 defm MVE_VQDMLSDH : MVE_VQxDMLxDH_multi<"vqdmlsdh", 0b0, 0b0, 0b1>;
4596 defm MVE_VQDMLSDHX : MVE_VQxDMLxDH_multi<"vqdmlsdhx", 0b1, 0b0, 0b1>;
4597 defm MVE_VQRDMLSDH : MVE_VQxDMLxDH_multi<"vqrdmlsdh", 0b0, 0b1, 0b1>;
4598 defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
4657 let Inst{16} = 0b1;
4699 int_arm_mve_mull_int_predicated, 0b1, 0b01>;
4703 int_arm_mve_mull_int_predicated, 0b1, 0b10>;
4708 int_arm_mve_mull_int_predicated, 0b1, 0b11,
4714 int_arm_mve_mull_int_predicated, 0b1, 0b01>;
4718 int_arm_mve_mull_int_predicated, 0b1, 0b10>;
4723 int_arm_mve_mull_int_predicated, 0b1, 0b11,
4729 int_arm_mve_mull_poly_predicated, 0b1, 0b01>;
4733 int_arm_mve_mull_poly_predicated, 0b1, 0b10>;
4789 let Inst{16} = 0b1;
4793 let Inst{0} = 0b1;
4837 defm MVE_VRMULHs8 : MVE_VMULT<"vrmulh", MVE_v16s8, 0b1>;
4838 defm MVE_VRMULHs16 : MVE_VMULT<"vrmulh", MVE_v8s16, 0b1>;
4839 defm MVE_VRMULHs32 : MVE_VMULT<"vrmulh", MVE_v4s32, 0b1>;
4840 defm MVE_VRMULHu8 : MVE_VMULT<"vrmulh", MVE_v16u8, 0b1>;
4841 defm MVE_VRMULHu16 : MVE_VMULT<"vrmulh", MVE_v8u16, 0b1>;
4842 defm MVE_VRMULHu32 : MVE_VMULT<"vrmulh", MVE_v4u32, 0b1>;
4854 let Inst{16} = 0b1;
4858 let Inst{0} = 0b1;
4866 def th : MVE_VxMOVxN<iname # "t", suffix, bit_28, bit_17, size, 0b1>;
4869 defm MVE_VMOVNi16 : MVE_VxMOVxN_halves<"vmovn", "i16", 0b1, 0b0, 0b00>;
4870 defm MVE_VMOVNi32 : MVE_VxMOVxN_halves<"vmovn", "i32", 0b1, 0b0, 0b01>;
4871 defm MVE_VQMOVNs16 : MVE_VxMOVxN_halves<"vqmovn", "s16", 0b0, 0b1, 0b00>;
4872 defm MVE_VQMOVNs32 : MVE_VxMOVxN_halves<"vqmovn", "s32", 0b0, 0b1, 0b01>;
4873 defm MVE_VQMOVNu16 : MVE_VxMOVxN_halves<"vqmovn", "u16", 0b1, 0b1, 0b00>;
4874 defm MVE_VQMOVNu32 : MVE_VxMOVxN_halves<"vqmovn", "u32", 0b1, 0b1, 0b01>;
4998 let Inst{0} = 0b1;
5030 def "": MVE_VCVT_ff<iname, "f32.f16", 0b1, half, (ins), vpred_r, "">;
5048 defm MVE_VCVTf16f32th : MVE_VCVT_f2h_m<"vcvtt", 0b1>;
5050 defm MVE_VCVTf32f16th : MVE_VCVT_h2f_m<"vcvtt", 0b1>;
5065 let Inst{8} = 0b1;
5092 defm MVE_VCADDi8 : MVE_VxCADD_m<"vcadd", MVE_v16i8, 0b1>;
5093 defm MVE_VCADDi16 : MVE_VxCADD_m<"vcadd", MVE_v8i16, 0b1>;
5094 defm MVE_VCADDi32 : MVE_VxCADD_m<"vcadd", MVE_v4i32, 0b1, "@earlyclobber $Qd">;
5112 let Inst{8} = 0b1;
5122 def MVE_VADCI : MVE_VADCSBC<"vadci", 0b1, 0b0, (ins)>;
5124 def MVE_VSBC : MVE_VADCSBC<"vsbc", 0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
5125 def MVE_VSBCI : MVE_VADCSBC<"vsbci", 0b1, 0b1, (ins)>;
5139 let Inst{8} = 0b1;
5141 let Inst{0} = 0b1;
5169 defm th : MVE_VQDMULL_m<"vqdmullt", VTI, size, 0b1, cstr>;
5173 defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<MVE_v4s32, 0b1, "@earlyclobber $Qd">;
5192 let Inst{6} = 0b1;
5253 let Inst{8} = 0b1;
5261 def "" : MVE_VADDSUB_qr<iname, VTI.Suffix, VTI.Size, 0b0, subtract, 0b1, 0b0>;
5271 : MVE_VADDSUB_qr_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>;
5284 def "" : MVE_VADDSUB_qr<iname, VTI.Suffix, VTI.Size, 0b1, subtract,
5297 : MVE_VQADDSUB_qr_m<"vqsub", VTI, 0b1, Op, int_arm_mve_qsub_predicated>;
5321 let Inst{8} = 0b1;
5322 let Inst{5} = 0b1;
5353 defm th : MVE_VQDMULL_qr_m<"vqdmullt", VTI, size, 0b1, cstr>;
5357 defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<MVE_v4s32, 0b1, "@earlyclobber $Qd">;
5368 let Inst{8} = 0b1;
5392 MVE_VHADDSUB_qr_m<"vhsub", VTI, 0b1, null_frag, int_arm_mve_vhsub,
5422 defm MVE_VSUB_qr_f32 : MVE_VADDSUB_qr_f<"vsub", MVE_v4f32, 0b1, fsub,
5424 defm MVE_VSUB_qr_f16 : MVE_VADDSUB_qr_f<"vsub", MVE_v8f16, 0b1, fsub,
5437 let Inst{16} = 0b1;
5471 defm MVE_VRSHL_qr : MVE_VxSHL_qr_types<"vrshl", 0b0, 0b1>;
5472 defm MVE_VQSHL_qr : MVE_VxSHL_qr_types<"vqshl", 0b1, 0b0>;
5473 defm MVE_VQRSHL_qr : MVE_VxSHL_qr_types<"vqrshl", 0b1, 0b1>;
5494 let Inst{28} = 0b1;
5496 let Inst{16} = 0b1;
5497 let Inst{12} = 0b1;
5499 let Inst{5} = 0b1;
5546 let Inst{16} = 0b1;
5547 let Inst{12} = 0b1;
5549 let Inst{5} = 0b1;
5571 let Inst{16} = 0b1;
5574 let Inst{5} = 0b1;
5593 MVE_VxxMUL_qr_m<"vqrdmulh", VTI, 0b1, null_frag,
5623 let Inst{16} = 0b1;
5661 defm MVE_VMLAS_qr_i8 : MVE_VMLA_qr_multi<"vmlas", MVE_v16i8, 0b1>;
5662 defm MVE_VMLAS_qr_i16 : MVE_VMLA_qr_multi<"vmlas", MVE_v8i16, 0b1>;
5663 defm MVE_VMLAS_qr_i32 : MVE_VMLA_qr_multi<"vmlas", MVE_v4i32, 0b1>;
5752 defm MVE_VQDMLAH_qr : MVE_VQDMLAH_qr_types<"vqdmlah", 0b1, 0b0>;
5754 defm MVE_VQDMLASH_qr : MVE_VQDMLAH_qr_types<"vqdmlash", 0b1, 0b1>;
5755 defm MVE_VQRDMLASH_qr : MVE_VQDMLAH_qr_types<"vqrdmlash", 0b0, 0b1>;
5773 let Inst{16} = 0b1;
5788 def MVE_VDDUPu8 : MVE_VxDUP<"vddup", "u8", 0b00, 0b1, v16i8, null_frag>;
5789 def MVE_VDDUPu16 : MVE_VxDUP<"vddup", "u16", 0b01, 0b1, v8i16, null_frag>;
5790 def MVE_VDDUPu32 : MVE_VxDUP<"vddup", "u32", 0b10, 0b1, v4i32, null_frag>;
5808 let Inst{16} = 0b1;
5824 def MVE_VDWDUPu8 : MVE_VxWDUP<"vdwdup", "u8", 0b00, 0b1>;
5825 def MVE_VDWDUPu16 : MVE_VxWDUP<"vdwdup", "u16", 0b01, 0b1>;
5826 def MVE_VDWDUPu32 : MVE_VxWDUP<"vdwdup", "u32", 0b10, 0b1>;
5921 0b1, "$Qd$idx, $QdSrc$idx2, $Rt, $Rt2",
6346 let Inst{23} = 0b1;
6595 let Inst{16} = 0b1;
6632 let Inst{0} = 0b1;
6642 let Inst{12} = 0b1;
6656 let Inst{6} = 0b1;
6676 let Inst{5} = 0b1;
6686 let Inst{12} = 0b1;
6707 let Inst{16} = 0b1;
6732 def MVE_VPTv8f16 : MVE_VPTft1<"f16", 0b1>;
6740 let Inst{6} = 0b1;
6746 def MVE_VPTv8f16r : MVE_VPTft2<"f16", 0b1>;
6757 let Unpredictable{12} = 0b1;
6758 let Unpredictable{7} = 0b1;
6759 let Unpredictable{5} = 0b1;
6771 let Inst{28} = 0b1;
6776 let Inst{16} = 0b1;
6779 let Inst{8} = 0b1;
6785 let Inst{0} = 0b1;
6885 let Unpredictable{12} = 0b1;
6886 let Unpredictable{7} = 0b1;
6887 let Unpredictable{5} = 0b1;
6917 let Inst{13} = 0b1;
6979 let Inst{20} = 0b1;
6989 let Inst{13} = 0b1;