1 //===- ARCInstrInfo.cpp - ARC Instruction Information -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
29 #define DEBUG_TYPE "arc-inst-info"
83 /// store to a stack slot, return the virtual or physical register number of
154 /// 3. If this block ends with a conditional branch and it falls through to a
158 /// 4. If this block ends with a conditional branch followed by an
179   --I;  in analyzeBranch()
181   while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {  in analyzeBranch()
188     while (I->isDebugInstr() || !I->isTerminator()) {  in analyzeBranch()
191       --I;  in analyzeBranch()
194     if (isJumpOpcode(I->getOpcode())) {  in analyzeBranch()
198     } else if (isUncondBranchOpcode(I->getOpcode())) {  in analyzeBranch()
199       TBB = I->getOperand(0).getMBB();  in analyzeBranch()
200     } else if (isCondBranchOpcode(I->getOpcode())) {  in analyzeBranch()
201       // Bail out if we encounter multiple conditional branches.  in analyzeBranch()
207       TBB = I->getOperand(0).getMBB();  in analyzeBranch()
208       Cond.push_back(I->getOperand(1));  in analyzeBranch()
209       Cond.push_back(I->getOperand(2));  in analyzeBranch()
210       Cond.push_back(I->getOperand(3));  in analyzeBranch()
211     } else if (I->isReturn()) {  in analyzeBranch()
219     // Cleanup code - to be run for unpredicated unconditional branches and  in analyzeBranch()
221     if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||  in analyzeBranch()
222                               isJumpOpcode(I->getOpcode()) || I->isReturn())) {  in analyzeBranch()
223       // Forget any previous condition branch information - it no longer  in analyzeBranch()
246     --I;  in analyzeBranch()
249   // We made it past the terminators without bailing out - we must have  in analyzeBranch()
261   if (!isUncondBranchOpcode(I->getOpcode()) &&  in removeBranch()
262       !isCondBranchOpcode(I->getOpcode()))  in removeBranch()
266   I->eraseFromParent();  in removeBranch()
272   --I;  in removeBranch()
273   if (!isCondBranchOpcode(I->getOpcode()))  in removeBranch()
277   I->eraseFromParent();  in removeBranch()
306   assert(MMO && "Couldn't get MachineMemOperand for store to stack.");  in storeRegToStackSlot()
307   assert(TRI->getSpillSize(*RC) == 4 &&  in storeRegToStackSlot()
308          "Only support 4-byte stores to stack now.");  in storeRegToStackSlot()
311   LLVM_DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI)  in storeRegToStackSlot()
334   assert(MMO && "Couldn't get MachineMemOperand for store to stack.");  in loadRegFromStackSlot()
335   assert(TRI->getSpillSize(*RC) == 4 &&  in loadRegFromStackSlot()
336          "Only support 4-byte loads from stack now.");  in loadRegFromStackSlot()
392   // One-way conditional branch.  in insertBranch()
397   // Two-way conditional branch.  in insertBranch()
404     const MachineFunction *MF = MI.getParent()->getParent();  in getInstSizeInBytes()
406     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());  in getInstSizeInBytes()