Lines Matching refs:b11
2952 let Inst{14-13} = 0b11;
3026 let Inst{14-13} = 0b11;
3098 let Unpredictable{15-14} = 0b11;
4419 let Inst{11-10} = 0b11;
4864 BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!",
4958 def UWHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR32, asm,
4965 def UXHr : BaseFPToIntegerUnscaled<0b11, rmode, opcode, FPR16, GPR64, asm,
4999 def SWHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR32,
5009 def SXHri : BaseFPToInteger<0b11, rmode, opcode, FPR16, GPR64,
5096 let Inst{23-22} = 0b11; // 16-bit FPR flag
5112 let Inst{23-22} = 0b11; // 16-bit FPR flag
5132 let Inst{23-22} = 0b11; // 16-bit FPR flag
5160 let Inst{23-22} = 0b11; // 16-bit FPR flag
5252 let Inst{23-22} = 0b11; // 16-bit FPR flag
5258 let Inst{23-22} = 0b11; // 16-bit FPR flag
5274 let Inst{23-22} = 0b11; // 16-bit FPR flag
5280 let Inst{23-22} = 0b11; // 16-bit FPR flag
5329 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
5337 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
5341 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
5349 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
5378 let Inst{23-22} = 0b11; // 16-bit size flag
5440 let Inst{23-22} = 0b11; // 16-bit size flag
5461 let Inst{23-22} = 0b11; // 16-bit size flag
5505 let Inst{23-22} = 0b11; // 16-bit size flag
5604 let Inst{23-22} = 0b11;
5610 let Inst{23-22} = 0b11;
5669 let Inst{23-22} = 0b11;
5706 let Inst{11-10} = 0b11;
5714 let Inst{23-22} = 0b11;
5747 let Inst{23-22} = 0b11;
5977 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
5980 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
5983 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
6000 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
6003 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
6006 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
6024 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0b01}, {0b11,opc}, V64,
6028 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0b01}, {0b11,opc}, V128,
6032 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128,
6167 def v8f16 : BaseSIMDThreeSameVectorDot<Q, 0b0, 0b11, 0b1111, asm, ".8h", ".16b",
6417 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, 0b00, V128,
6442 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, 0b00, V128,
6484 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
6487 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
6542 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
6545 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
6564 def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
6567 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
6713 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128,
6724 def v4i16rz : BaseSIMDCmpTwoVector<0, U, {S,1}, 0b11, opc, V64,
6727 def v8i16rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b11, opc, V128,
7400 def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
7402 def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
7418 def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
7420 def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
7563 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, 0b00, opc, FPR64, asm, "0">;
7575 def v1i16rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b11, opc, FPR16, asm, "0.0">;
7595 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
7611 def v1f16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,[]>;
7625 def v1i16 : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,
7633 def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
7648 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
7696 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
8150 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
8158 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
8194 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
8202 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
8263 …def v8f16 : BaseSIMDTableLookupIndexed<0b1, {0b11,?,?,?}, V128, VecListOne8h, VectorIndexH, asm, "…
8721 def v8f16 : BaseSIMDThreeSameVectorIndexB<Q, 0b0, 0b11, 0b0000, asm, ".8h",
8872 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
8911 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
9063 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
9091 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
10446 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
10475 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
10519 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
10547 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
10584 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
10588 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
10604 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
10608 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
10774 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
10776 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
10797 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
10800 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
11386 def v2f64 : BaseSIMDThreeSameVectorComplex<1, U, 0b11, opcode, V128, rottype,
11458 def v2f64 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b11, opcode, V128,
11798 let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseCAS<order, "", GPR64>;
11846 let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseSWP<order, "", GPR64>;
11883 let Sz = 0b11, Acq = Acq, Rel = Rel, opc = opc in
12089 def N : MOPSMemoryCopy<opcode, 0b00, 0b11, asm # "n">;
12093 def WTN : MOPSMemoryCopy<opcode, 0b01, 0b11, asm # "wtn">;
12097 def RTN : MOPSMemoryCopy<opcode, 0b10, 0b11, asm # "rtn">;
12098 def T : MOPSMemoryCopy<opcode, 0b11, 0b00, asm # "t">;
12099 def TWN : MOPSMemoryCopy<opcode, 0b11, 0b01, asm # "twn">;
12100 def TRN : MOPSMemoryCopy<opcode, 0b11, 0b10, asm # "trn">;
12101 def TN : MOPSMemoryCopy<opcode, 0b11, 0b11, asm # "tn">;
12108 def N : MOPSMemoryMove<opcode, 0b00, 0b11, asm # "n">;
12112 def WTN : MOPSMemoryMove<opcode, 0b01, 0b11, asm # "wtn">;
12116 def RTN : MOPSMemoryMove<opcode, 0b10, 0b11, asm # "rtn">;
12117 def T : MOPSMemoryMove<opcode, 0b11, 0b00, asm # "t">;
12118 def TWN : MOPSMemoryMove<opcode, 0b11, 0b01, asm # "twn">;
12119 def TRN : MOPSMemoryMove<opcode, 0b11, 0b10, asm # "trn">;
12120 def TN : MOPSMemoryMove<opcode, 0b11, 0b11, asm # "tn">;