| c5ad454a | 14-Nov-2022 |
Gayatri Kammela <gayatri.kammela@linux.intel.com> |
platform/x86: intel/pmc/core: Add Meteor Lake support to pmc core driver
Add Meteor Lake client and mobile support to pmc core driver. This patch adds legacy support.
Cc: David E Box <david.e.box@l
platform/x86: intel/pmc/core: Add Meteor Lake support to pmc core driver
Add Meteor Lake client and mobile support to pmc core driver. This patch adds legacy support.
Cc: David E Box <david.e.box@linux.intel.com> Suggested-by: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@linux.intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-9-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 08876884 | 14-Nov-2022 |
Gayatri Kammela <gayatri.kammela@linux.intel.com> |
platform/x86: intel/pmc: Relocate Alder Lake PCH support
Create adl.c for Alder Lake PCH specific structures and init(). This file supports Alder Lake, Raptor Lake and Raptor Lake S platforms There
platform/x86: intel/pmc: Relocate Alder Lake PCH support
Create adl.c for Alder Lake PCH specific structures and init(). This file supports Alder Lake, Raptor Lake and Raptor Lake S platforms There are no functional changes involved.
Cc: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@linux.intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-8-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 92f530ed | 14-Nov-2022 |
Gayatri Kammela <gayatri.kammela@linux.intel.com> |
platform/x86: intel/pmc: Relocate Tiger Lake PCH support
Create tgl.c for Tiger Lake PCH specific structures and init(). This file supports Tiger Lake, Elkhart Lake, Rocket Lake, Alder Lake mobile,
platform/x86: intel/pmc: Relocate Tiger Lake PCH support
Create tgl.c for Tiger Lake PCH specific structures and init(). This file supports Tiger Lake, Elkhart Lake, Rocket Lake, Alder Lake mobile, Alder Lake N and Raptor Lake P platforms. There are no functional changes involved.
Cc: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@linux.intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-7-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| fd2ed6db | 14-Nov-2022 |
Xi Pardee <xi.pardee@intel.com> |
platform/x86: intel/pmc: Relocate Ice Lake PCH support
Create icl.c for Ice Lake PCH specific structures and init(). This file supports Ice Lake, Ice Lake NNPI and Jasper Lake platforms. There are n
platform/x86: intel/pmc: Relocate Ice Lake PCH support
Create icl.c for Ice Lake PCH specific structures and init(). This file supports Ice Lake, Ice Lake NNPI and Jasper Lake platforms. There are no functional changes involved.
Cc: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Xi Pardee <xi.pardee@intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-6-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| d6cd0cc8 | 14-Nov-2022 |
Xi Pardee <xi.pardee@intel.com> |
platform/x86: intel/pmc: Relocate Cannon Lake Point PCH support
Create cnp.c for Cannon Lake Point PCH specific structures and init(). This file supports Cannon Lake and Comet Lake platforms. There
platform/x86: intel/pmc: Relocate Cannon Lake Point PCH support
Create cnp.c for Cannon Lake Point PCH specific structures and init(). This file supports Cannon Lake and Comet Lake platforms. There are no functional changes involved.
Cc: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Xi Pardee <xi.pardee@intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-5-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| f23e21a3 | 14-Nov-2022 |
Rajvi Jingar <rajvi.jingar@linux.intel.com> |
platform/x86: intel/pmc: Relocate Sunrise Point PCH support
Create spt.c for Sunrise Point PCH specific structures and init(). This file supports Sky Lake and Kaby Lake platforms. There are no funct
platform/x86: intel/pmc: Relocate Sunrise Point PCH support
Create spt.c for Sunrise Point PCH specific structures and init(). This file supports Sky Lake and Kaby Lake platforms. There are no functional changes involved.
Cc: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-4-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 03c58a1e | 14-Nov-2022 |
Xi Pardee <xi.pardee@intel.com> |
platform/x86: intel/pmc: Move variable declarations and definitions to header and core.c
Move the msr_map variable declaration to core.h and move the pmc_lpm_modes definition to core.c.
This is a p
platform/x86: intel/pmc: Move variable declarations and definitions to header and core.c
Move the msr_map variable declaration to core.h and move the pmc_lpm_modes definition to core.c.
This is a prepartory patch for redesigning the pmc core driver as the variables will be used in multiple PCH specific files.
Cc: David E Box <david.e.box@linux.intel.com> Reviewed-by: "David E. Box" <david.e.box@linux.intel.com> Signed-off-by: Xi Pardee <xi.pardee@intel.com> Signed-off-by: "David E. Box" <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20221114183257.2067662-3-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 2dbfb3f3 | 10-Nov-2022 |
Roger Pau Monné <roger.pau@citrix.com> |
platform/x86/intel: pmc: Don't unconditionally attach Intel PMC when virtualized
The current logic in the Intel PMC driver will forcefully attach it when detecting any CPU on the intel_pmc_core_plat
platform/x86/intel: pmc: Don't unconditionally attach Intel PMC when virtualized
The current logic in the Intel PMC driver will forcefully attach it when detecting any CPU on the intel_pmc_core_platform_ids array, even if the matching ACPI device is not present.
There's no checking in pmc_core_probe() to assert that the PMC device is present, and hence on virtualized environments the PMC device probes successfully, even if the underlying registers are not present. Before commit 21ae43570940 ("platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration") the driver would check for the presence of a specific PCI device, and that prevented the driver from attaching when running virtualized.
Fix by only forcefully attaching the PMC device when not running virtualized. Note that virtualized platforms can still get the device to load if the appropriate ACPI device is present on the tables provided to the VM.
Make an exception for the Xen initial domain, which does have full hardware access, and hence can attach to the PMC if present.
Fixes: 21ae43570940 ("platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration") Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Acked-by: David E. Box <david.e.box@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221110163145.80374-1-roger.pau@citrix.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| d63eae67 | 15-Jun-2022 |
Gayatri Kammela <gayatri.kammela@linux.intel.com> |
platform/x86: intel/pmc: Add Alder Lake N support to PMC core driver
Add Alder Lake N (ADL-N) to the list of the platforms that Intel's PMC core driver supports. Alder Lake N reuses all the TigerLak
platform/x86: intel/pmc: Add Alder Lake N support to PMC core driver
Add Alder Lake N (ADL-N) to the list of the platforms that Intel's PMC core driver supports. Alder Lake N reuses all the TigerLake PCH IPs.
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: David E. Box <david.e.box@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@linux.intel.com> Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Link: https://lore.kernel.org/r/20220615002751.3371730-1-gayatri.kammela@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 0eb369bf | 25-Apr-2022 |
Minghao Chi <chi.minghao@zte.com.cn> |
platform/x86/intel: pmc/core: Use kobj_to_dev()
Use kobj_to_dev() instead of open-coding it.
Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Link: ht
platform/x86/intel: pmc/core: Use kobj_to_dev()
Use kobj_to_dev() instead of open-coding it.
Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220425105525.3515831-1-chi.minghao@zte.com.cn Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 66a91c00 | 16-Aug-2021 |
David E. Box <david.e.box@linux.intel.com> |
platform/x86/intel: pmc/core: Add GBE Package C10 fix for Alder Lake PCH
Alder PCH uses the same Gigabit Ethernet (GBE) device as Tiger Lake PCH which cannot achieve PC10 without ignoring the PMC GB
platform/x86/intel: pmc/core: Add GBE Package C10 fix for Alder Lake PCH
Alder PCH uses the same Gigabit Ethernet (GBE) device as Tiger Lake PCH which cannot achieve PC10 without ignoring the PMC GBE LTR. Add this work around for Alder Lake PCH as well.
Cc: Chao Qin <chao.qin@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: You-Sheng Yang <vicamo.yang@canonical.com> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: David E. Box <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/9168e8bd687f2d0d5eb0ed116e08d0764eadf7b3.1629091915.git.gayatri.kammela@intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| 6cfce3ef | 16-Aug-2021 |
Gayatri Kammela <gayatri.kammela@intel.com> |
platform/x86/intel: pmc/core: Add Alder Lake low power mode support for pmc core
Alder Lake has 14 status registers that are memory mapped. These registers show the status of the low power mode requ
platform/x86/intel: pmc/core: Add Alder Lake low power mode support for pmc core
Alder Lake has 14 status registers that are memory mapped. These registers show the status of the low power mode requirements. The registers are latched on every C10 entry or exit and on every s0ix.y entry/exit. Accessing these registers is useful for debugging any low power related activities.
Thus, add debugfs entry to access low power mode status registers.
Cc: Chao Qin <chao.qin@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: David Box <david.e.box@intel.com> Tested-by: You-Sheng Yang <vicamo.yang@canonical.com> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Link: https://lore.kernel.org/r/d27ec98589a5aaa569bbce0e937ed03779fc0a22.1629091915.git.gayatri.kammela@intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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| ee7e89ff | 16-Aug-2021 |
Gayatri Kammela <gayatri.kammela@intel.com> |
platform/x86/intel: pmc/core: Add Latency Tolerance Reporting (LTR) support to Alder Lake
Add support to show the Latency Tolerance Reporting for the IPs on the Alder Lake PCH as reported by the PMC
platform/x86/intel: pmc/core: Add Latency Tolerance Reporting (LTR) support to Alder Lake
Add support to show the Latency Tolerance Reporting for the IPs on the Alder Lake PCH as reported by the PMC. This LTR support on Alder Lake is slightly different from the Cannon lake PCH that is being reused by all platforms till Tiger Lake.
Cc: Chao Qin <chao.qin@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: David Box <david.e.box@intel.com> Tested-by: You-Sheng Yang <vicamo.yang@canonical.com> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Link: https://lore.kernel.org/r/5ca3ea090b53a9bf918b055447ab5c8ef2925cc4.1629091915.git.gayatri.kammela@intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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