gpio-zynq.c (20a8a96873f69dc915e872e291f4376f436b295a) gpio-zynq.c (bdf7a4ae371894b4dc10b5820006b0a82d484929)
1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later

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13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later

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13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/of.h>
21
22#define DRIVER_NAME "zynq-gpio"
23
24/* Maximum banks */
25#define ZYNQ_GPIO_MAX_BANK 4
22
23#define DRIVER_NAME "zynq-gpio"
24
25/* Maximum banks */
26#define ZYNQ_GPIO_MAX_BANK 4
27#define ZYNQMP_GPIO_MAX_BANK 6
26
27#define ZYNQ_GPIO_BANK0_NGPIO 32
28#define ZYNQ_GPIO_BANK1_NGPIO 22
29#define ZYNQ_GPIO_BANK2_NGPIO 32
30#define ZYNQ_GPIO_BANK3_NGPIO 32
31
28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
32#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
33 ZYNQ_GPIO_BANK1_NGPIO + \
34 ZYNQ_GPIO_BANK2_NGPIO + \
35 ZYNQ_GPIO_BANK3_NGPIO)
34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
36
40
37#define ZYNQ_GPIO_BANK0_PIN_MIN 0
38#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
39 ZYNQ_GPIO_BANK0_NGPIO - 1)
40#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
41#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
42 ZYNQ_GPIO_BANK1_NGPIO - 1)
43#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
44#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
45 ZYNQ_GPIO_BANK2_NGPIO - 1)
46#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
47#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
48 ZYNQ_GPIO_BANK3_NGPIO - 1)
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
49
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
50
62
63
51/* Register offsets for the GPIO device */
52/* LSW Mask & Data -WO */
53#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
54/* MSW Mask & Data -WO */
55#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
56/* Data Register-RW */
57#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
58/* Direction mode reg-RW */

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84#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
85
86/**
87 * struct zynq_gpio - gpio device private data structure
88 * @chip: instance of the gpio_chip
89 * @base_addr: base address of the GPIO device
90 * @clk: clock resource for this controller
91 * @irq: interrupt for the GPIO device
64/* Register offsets for the GPIO device */
65/* LSW Mask & Data -WO */
66#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
67/* MSW Mask & Data -WO */
68#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
69/* Data Register-RW */
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */

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97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
99/**
100 * struct zynq_gpio - gpio device private data structure
101 * @chip: instance of the gpio_chip
102 * @base_addr: base address of the GPIO device
103 * @clk: clock resource for this controller
104 * @irq: interrupt for the GPIO device
105 * @p_data: pointer to platform data
92 */
93struct zynq_gpio {
94 struct gpio_chip chip;
95 void __iomem *base_addr;
96 struct clk *clk;
97 int irq;
106 */
107struct zynq_gpio {
108 struct gpio_chip chip;
109 void __iomem *base_addr;
110 struct clk *clk;
111 int irq;
112 const struct zynq_platform_data *p_data;
98};
99
113};
114
115/**
116 * struct zynq_platform_data - zynq gpio platform data structure
117 * @label: string to store in gpio->label
118 * @ngpio: max number of gpio pins
119 * @max_bank: maximum number of gpio banks
120 * @bank_min: this array represents bank's min pin
121 * @bank_max: this array represents bank's max pin
122*/
123struct zynq_platform_data {
124 const char *label;
125 u16 ngpio;
126 int max_bank;
127 int bank_min[ZYNQMP_GPIO_MAX_BANK];
128 int bank_max[ZYNQMP_GPIO_MAX_BANK];
129};
130
100static struct irq_chip zynq_gpio_level_irqchip;
101static struct irq_chip zynq_gpio_edge_irqchip;
102/**
103 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
104 * for a given pin in the GPIO device
105 * @pin_num: gpio pin number within the device
106 * @bank_num: an output parameter used to return the bank number of the gpio
107 * pin
108 * @bank_pin_num: an output parameter used to return pin number within a bank
109 * for the given gpio pin
110 *
111 * Returns the bank number and pin offset within the bank.
112 */
113static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
114 unsigned int *bank_num,
131static struct irq_chip zynq_gpio_level_irqchip;
132static struct irq_chip zynq_gpio_edge_irqchip;
133/**
134 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
135 * for a given pin in the GPIO device
136 * @pin_num: gpio pin number within the device
137 * @bank_num: an output parameter used to return the bank number of the gpio
138 * pin
139 * @bank_pin_num: an output parameter used to return pin number within a bank
140 * for the given gpio pin
141 *
142 * Returns the bank number and pin offset within the bank.
143 */
144static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
145 unsigned int *bank_num,
115 unsigned int *bank_pin_num)
146 unsigned int *bank_pin_num,
147 struct zynq_gpio *gpio)
116{
148{
117 switch (pin_num) {
118 case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
119 *bank_num = 0;
120 *bank_pin_num = pin_num;
121 break;
122 case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
123 *bank_num = 1;
124 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
125 break;
126 case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
127 *bank_num = 2;
128 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
129 break;
130 case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
131 *bank_num = 3;
132 *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
133 break;
134 default:
135 WARN(true, "invalid GPIO pin number: %u", pin_num);
136 *bank_num = 0;
137 *bank_pin_num = 0;
138 break;
149 int bank;
150
151 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
152 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
153 (pin_num <= gpio->p_data->bank_max[bank])) {
154 *bank_num = bank;
155 *bank_pin_num = pin_num -
156 gpio->p_data->bank_min[bank];
157 return;
158 }
139 }
159 }
160
161 /* default */
162 WARN(true, "invalid GPIO pin number: %u", pin_num);
163 *bank_num = 0;
164 *bank_pin_num = 0;
140}
141
165}
166
142static const unsigned int zynq_gpio_bank_offset[] = {
143 ZYNQ_GPIO_BANK0_PIN_MIN,
144 ZYNQ_GPIO_BANK1_PIN_MIN,
145 ZYNQ_GPIO_BANK2_PIN_MIN,
146 ZYNQ_GPIO_BANK3_PIN_MIN,
147};
148
149/**
150 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
151 * @chip: gpio_chip instance to be worked on
152 * @pin: gpio pin number within the device
153 *
154 * This function reads the state of the specified pin of the GPIO device.
155 *
156 * Return: 0 if the pin is low, 1 if pin is high.
157 */
158static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
159{
160 u32 data;
161 unsigned int bank_num, bank_pin_num;
162 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
163
167/**
168 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
169 * @chip: gpio_chip instance to be worked on
170 * @pin: gpio pin number within the device
171 *
172 * This function reads the state of the specified pin of the GPIO device.
173 *
174 * Return: 0 if the pin is low, 1 if pin is high.
175 */
176static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
177{
178 u32 data;
179 unsigned int bank_num, bank_pin_num;
180 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
181
164 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
182 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
165
166 data = readl_relaxed(gpio->base_addr +
167 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
168
169 return (data >> bank_pin_num) & 1;
170}
171
172/**

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180 * gpio pin to the specified value. The state is either 0 or non-zero.
181 */
182static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
183 int state)
184{
185 unsigned int reg_offset, bank_num, bank_pin_num;
186 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
187
183
184 data = readl_relaxed(gpio->base_addr +
185 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
186
187 return (data >> bank_pin_num) & 1;
188}
189
190/**

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198 * gpio pin to the specified value. The state is either 0 or non-zero.
199 */
200static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
201 int state)
202{
203 unsigned int reg_offset, bank_num, bank_pin_num;
204 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
205
188 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
206 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
189
190 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
191 /* only 16 data bits in bit maskable reg */
192 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
193 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
194 } else {
195 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
196 }

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217 * Return: 0 always
218 */
219static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
220{
221 u32 reg;
222 unsigned int bank_num, bank_pin_num;
223 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
224
207
208 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
209 /* only 16 data bits in bit maskable reg */
210 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
211 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
212 } else {
213 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
214 }

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235 * Return: 0 always
236 */
237static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
238{
239 u32 reg;
240 unsigned int bank_num, bank_pin_num;
241 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
242
225 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
243 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
226
227 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
228 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
229 return -EINVAL;
230
231 /* clear the bit in direction mode reg to set the pin as input */
232 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
233 reg &= ~BIT(bank_pin_num);

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250 */
251static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
252 int state)
253{
254 u32 reg;
255 unsigned int bank_num, bank_pin_num;
256 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
257
244
245 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
246 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
247 return -EINVAL;
248
249 /* clear the bit in direction mode reg to set the pin as input */
250 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
251 reg &= ~BIT(bank_pin_num);

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268 */
269static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
270 int state)
271{
272 u32 reg;
273 unsigned int bank_num, bank_pin_num;
274 struct zynq_gpio *gpio = container_of(chip, struct zynq_gpio, chip);
275
258 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num);
276 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
259
260 /* set the GPIO pin as output */
261 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
262 reg |= BIT(bank_pin_num);
263 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
264
265 /* configure the output enable reg for the pin */
266 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));

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281 * interrupts for that pin.
282 */
283static void zynq_gpio_irq_mask(struct irq_data *irq_data)
284{
285 unsigned int device_pin_num, bank_num, bank_pin_num;
286 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
287
288 device_pin_num = irq_data->hwirq;
277
278 /* set the GPIO pin as output */
279 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
280 reg |= BIT(bank_pin_num);
281 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
282
283 /* configure the output enable reg for the pin */
284 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));

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299 * interrupts for that pin.
300 */
301static void zynq_gpio_irq_mask(struct irq_data *irq_data)
302{
303 unsigned int device_pin_num, bank_num, bank_pin_num;
304 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
305
306 device_pin_num = irq_data->hwirq;
289 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
307 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
290 writel_relaxed(BIT(bank_pin_num),
291 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
292}
293
294/**
295 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
296 * @irq_data: irq data containing irq number of gpio pin for the interrupt
297 * to enable
298 *
299 * This function calculates the gpio pin number from irq number and sets the
300 * bit in the Interrupt Enable register of the corresponding bank to enable
301 * interrupts for that pin.
302 */
303static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
304{
305 unsigned int device_pin_num, bank_num, bank_pin_num;
306 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
307
308 device_pin_num = irq_data->hwirq;
308 writel_relaxed(BIT(bank_pin_num),
309 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
310}
311
312/**
313 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
314 * @irq_data: irq data containing irq number of gpio pin for the interrupt
315 * to enable
316 *
317 * This function calculates the gpio pin number from irq number and sets the
318 * bit in the Interrupt Enable register of the corresponding bank to enable
319 * interrupts for that pin.
320 */
321static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
322{
323 unsigned int device_pin_num, bank_num, bank_pin_num;
324 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
325
326 device_pin_num = irq_data->hwirq;
309 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
327 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
310 writel_relaxed(BIT(bank_pin_num),
311 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
312}
313
314/**
315 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
316 * @irq_data: irq data containing irq number of gpio pin for the interrupt
317 * to ack
318 *
319 * This function calculates gpio pin number from irq number and sets the bit
320 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
321 */
322static void zynq_gpio_irq_ack(struct irq_data *irq_data)
323{
324 unsigned int device_pin_num, bank_num, bank_pin_num;
325 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
326
327 device_pin_num = irq_data->hwirq;
328 writel_relaxed(BIT(bank_pin_num),
329 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
330}
331
332/**
333 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
334 * @irq_data: irq data containing irq number of gpio pin for the interrupt
335 * to ack
336 *
337 * This function calculates gpio pin number from irq number and sets the bit
338 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
339 */
340static void zynq_gpio_irq_ack(struct irq_data *irq_data)
341{
342 unsigned int device_pin_num, bank_num, bank_pin_num;
343 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
344
345 device_pin_num = irq_data->hwirq;
328 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
346 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
329 writel_relaxed(BIT(bank_pin_num),
330 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
331}
332
333/**
334 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
335 * @irq_data: irq data containing irq number of gpio pin for the interrupt
336 * to enable

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370 */
371static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
372{
373 u32 int_type, int_pol, int_any;
374 unsigned int device_pin_num, bank_num, bank_pin_num;
375 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
376
377 device_pin_num = irq_data->hwirq;
347 writel_relaxed(BIT(bank_pin_num),
348 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
349}
350
351/**
352 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
353 * @irq_data: irq data containing irq number of gpio pin for the interrupt
354 * to enable

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388 */
389static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
390{
391 u32 int_type, int_pol, int_any;
392 unsigned int device_pin_num, bank_num, bank_pin_num;
393 struct zynq_gpio *gpio = irq_data_get_irq_chip_data(irq_data);
394
395 device_pin_num = irq_data->hwirq;
378 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num);
396 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
379
380 int_type = readl_relaxed(gpio->base_addr +
381 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
382 int_pol = readl_relaxed(gpio->base_addr +
383 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
384 int_any = readl_relaxed(gpio->base_addr +
385 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
386

--- 78 unchanged lines hidden (view full) ---

465 .irq_set_wake = zynq_gpio_set_wake,
466 .flags = IRQCHIP_MASK_ON_SUSPEND,
467};
468
469static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
470 unsigned int bank_num,
471 unsigned long pending)
472{
397
398 int_type = readl_relaxed(gpio->base_addr +
399 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
400 int_pol = readl_relaxed(gpio->base_addr +
401 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
402 int_any = readl_relaxed(gpio->base_addr +
403 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
404

--- 78 unchanged lines hidden (view full) ---

483 .irq_set_wake = zynq_gpio_set_wake,
484 .flags = IRQCHIP_MASK_ON_SUSPEND,
485};
486
487static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
488 unsigned int bank_num,
489 unsigned long pending)
490{
473 unsigned int bank_offset = zynq_gpio_bank_offset[bank_num];
491 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
474 struct irq_domain *irqdomain = gpio->chip.irqdomain;
475 int offset;
476
477 if (!pending)
478 return;
479
480 for_each_set_bit(offset, &pending, 32) {
481 unsigned int gpio_irq;

--- 18 unchanged lines hidden (view full) ---

500{
501 u32 int_sts, int_enb;
502 unsigned int bank_num;
503 struct zynq_gpio *gpio = irq_get_handler_data(irq);
504 struct irq_chip *irqchip = irq_desc_get_chip(desc);
505
506 chained_irq_enter(irqchip, desc);
507
492 struct irq_domain *irqdomain = gpio->chip.irqdomain;
493 int offset;
494
495 if (!pending)
496 return;
497
498 for_each_set_bit(offset, &pending, 32) {
499 unsigned int gpio_irq;

--- 18 unchanged lines hidden (view full) ---

518{
519 u32 int_sts, int_enb;
520 unsigned int bank_num;
521 struct zynq_gpio *gpio = irq_get_handler_data(irq);
522 struct irq_chip *irqchip = irq_desc_get_chip(desc);
523
524 chained_irq_enter(irqchip, desc);
525
508 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++) {
526 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
509 int_sts = readl_relaxed(gpio->base_addr +
510 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
511 int_enb = readl_relaxed(gpio->base_addr +
512 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
513 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
514 }
515
516 chained_irq_exit(irqchip, desc);

--- 60 unchanged lines hidden (view full) ---

577}
578
579static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
580 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
581 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
582 zynq_gpio_runtime_resume, NULL)
583};
584
527 int_sts = readl_relaxed(gpio->base_addr +
528 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
529 int_enb = readl_relaxed(gpio->base_addr +
530 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
531 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
532 }
533
534 chained_irq_exit(irqchip, desc);

--- 60 unchanged lines hidden (view full) ---

595}
596
597static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
598 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
599 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
600 zynq_gpio_runtime_resume, NULL)
601};
602
603static const struct zynq_platform_data zynqmp_gpio_def = {
604 .label = "zynqmp_gpio",
605 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
606 .max_bank = ZYNQMP_GPIO_MAX_BANK,
607 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
608 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
609 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
610 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
611 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
612 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
613 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
614 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
615 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
616 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
617 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
618 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
619};
620
621static const struct zynq_platform_data zynq_gpio_def = {
622 .label = "zynq_gpio",
623 .ngpio = ZYNQ_GPIO_NR_GPIOS,
624 .max_bank = ZYNQ_GPIO_MAX_BANK,
625 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
626 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
627 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
628 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
629 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
630 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
631 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
632 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
633};
634
635static const struct of_device_id zynq_gpio_of_match[] = {
636 { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def },
637 { .compatible = "xlnx,zynqmp-gpio-1.0",
638 .data = (void *)&zynqmp_gpio_def },
639 { /* end of table */ }
640};
641MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
642
585/**
586 * zynq_gpio_probe - Initialization method for a zynq_gpio device
587 * @pdev: platform device instance
588 *
589 * This function allocates memory resources for the gpio device and registers
590 * all the banks of the device. It will also set up interrupts for the gpio
591 * pins.
592 * Note: Interrupts are disabled for all the banks during initialization.
593 *
594 * Return: 0 on success, negative error otherwise.
595 */
596static int zynq_gpio_probe(struct platform_device *pdev)
597{
598 int ret, bank_num;
599 struct zynq_gpio *gpio;
600 struct gpio_chip *chip;
601 struct resource *res;
643/**
644 * zynq_gpio_probe - Initialization method for a zynq_gpio device
645 * @pdev: platform device instance
646 *
647 * This function allocates memory resources for the gpio device and registers
648 * all the banks of the device. It will also set up interrupts for the gpio
649 * pins.
650 * Note: Interrupts are disabled for all the banks during initialization.
651 *
652 * Return: 0 on success, negative error otherwise.
653 */
654static int zynq_gpio_probe(struct platform_device *pdev)
655{
656 int ret, bank_num;
657 struct zynq_gpio *gpio;
658 struct gpio_chip *chip;
659 struct resource *res;
660 const struct of_device_id *match;
602
603 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
604 if (!gpio)
605 return -ENOMEM;
606
661
662 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
663 if (!gpio)
664 return -ENOMEM;
665
666 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
667 if (!match) {
668 dev_err(&pdev->dev, "of_match_node() failed\n");
669 return -EINVAL;
670 }
671 gpio->p_data = match->data;
607 platform_set_drvdata(pdev, gpio);
608
609 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
610 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
611 if (IS_ERR(gpio->base_addr))
612 return PTR_ERR(gpio->base_addr);
613
614 gpio->irq = platform_get_irq(pdev, 0);
615 if (gpio->irq < 0) {
616 dev_err(&pdev->dev, "invalid IRQ\n");
617 return gpio->irq;
618 }
619
620 /* configure the gpio chip */
621 chip = &gpio->chip;
672 platform_set_drvdata(pdev, gpio);
673
674 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
675 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
676 if (IS_ERR(gpio->base_addr))
677 return PTR_ERR(gpio->base_addr);
678
679 gpio->irq = platform_get_irq(pdev, 0);
680 if (gpio->irq < 0) {
681 dev_err(&pdev->dev, "invalid IRQ\n");
682 return gpio->irq;
683 }
684
685 /* configure the gpio chip */
686 chip = &gpio->chip;
622 chip->label = "zynq_gpio";
687 chip->label = gpio->p_data->label;
623 chip->owner = THIS_MODULE;
624 chip->dev = &pdev->dev;
625 chip->get = zynq_gpio_get_value;
626 chip->set = zynq_gpio_set_value;
627 chip->request = zynq_gpio_request;
628 chip->free = zynq_gpio_free;
629 chip->direction_input = zynq_gpio_dir_in;
630 chip->direction_output = zynq_gpio_dir_out;
631 chip->base = -1;
688 chip->owner = THIS_MODULE;
689 chip->dev = &pdev->dev;
690 chip->get = zynq_gpio_get_value;
691 chip->set = zynq_gpio_set_value;
692 chip->request = zynq_gpio_request;
693 chip->free = zynq_gpio_free;
694 chip->direction_input = zynq_gpio_dir_in;
695 chip->direction_output = zynq_gpio_dir_out;
696 chip->base = -1;
632 chip->ngpio = ZYNQ_GPIO_NR_GPIOS;
697 chip->ngpio = gpio->p_data->ngpio;
633
634 /* Enable GPIO clock */
635 gpio->clk = devm_clk_get(&pdev->dev, NULL);
636 if (IS_ERR(gpio->clk)) {
637 dev_err(&pdev->dev, "input clock not found.\n");
638 return PTR_ERR(gpio->clk);
639 }
640 ret = clk_prepare_enable(gpio->clk);

--- 5 unchanged lines hidden (view full) ---

646 /* report a bug if gpio chip registration fails */
647 ret = gpiochip_add(chip);
648 if (ret) {
649 dev_err(&pdev->dev, "Failed to add gpio chip\n");
650 goto err_disable_clk;
651 }
652
653 /* disable interrupts for all banks */
698
699 /* Enable GPIO clock */
700 gpio->clk = devm_clk_get(&pdev->dev, NULL);
701 if (IS_ERR(gpio->clk)) {
702 dev_err(&pdev->dev, "input clock not found.\n");
703 return PTR_ERR(gpio->clk);
704 }
705 ret = clk_prepare_enable(gpio->clk);

--- 5 unchanged lines hidden (view full) ---

711 /* report a bug if gpio chip registration fails */
712 ret = gpiochip_add(chip);
713 if (ret) {
714 dev_err(&pdev->dev, "Failed to add gpio chip\n");
715 goto err_disable_clk;
716 }
717
718 /* disable interrupts for all banks */
654 for (bank_num = 0; bank_num < ZYNQ_GPIO_MAX_BANK; bank_num++)
719 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
655 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
656 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
657
658 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
659 handle_level_irq, IRQ_TYPE_NONE);
660 if (ret) {
661 dev_err(&pdev->dev, "Failed to add irq chip\n");
662 goto err_rm_gpiochip;

--- 27 unchanged lines hidden (view full) ---

690
691 pm_runtime_get_sync(&pdev->dev);
692 gpiochip_remove(&gpio->chip);
693 clk_disable_unprepare(gpio->clk);
694 device_set_wakeup_capable(&pdev->dev, 0);
695 return 0;
696}
697
720 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
721 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
722
723 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
724 handle_level_irq, IRQ_TYPE_NONE);
725 if (ret) {
726 dev_err(&pdev->dev, "Failed to add irq chip\n");
727 goto err_rm_gpiochip;

--- 27 unchanged lines hidden (view full) ---

755
756 pm_runtime_get_sync(&pdev->dev);
757 gpiochip_remove(&gpio->chip);
758 clk_disable_unprepare(gpio->clk);
759 device_set_wakeup_capable(&pdev->dev, 0);
760 return 0;
761}
762
698static struct of_device_id zynq_gpio_of_match[] = {
699 { .compatible = "xlnx,zynq-gpio-1.0", },
700 { /* end of table */ }
701};
702MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
703
704static struct platform_driver zynq_gpio_driver = {
705 .driver = {
706 .name = DRIVER_NAME,
707 .pm = &zynq_gpio_dev_pm_ops,
708 .of_match_table = zynq_gpio_of_match,
709 },
710 .probe = zynq_gpio_probe,
711 .remove = zynq_gpio_remove,

--- 16 unchanged lines hidden --- 		763static struct platform_driver zynq_gpio_driver = {
764 .driver = {
765 .name = DRIVER_NAME,
766 .pm = &zynq_gpio_dev_pm_ops,
767 .of_match_table = zynq_gpio_of_match,
768 },
769 .probe = zynq_gpio_probe,
770 .remove = zynq_gpio_remove,

--- 16 unchanged lines hidden ---