gpio-mxs.c (8c31b1635b91e48f867e010cd7bcd06393e5858a) gpio-mxs.c (06f88a8ae9085e555baf81edbf967764d87dc12f)
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or

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22
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or

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22
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30#include <linux/basic_mmio_gpio.h>
30#include <mach/mxs.h>
31
32#define MXS_SET 0x4
33#define MXS_CLR 0x8
34
35#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
36#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
37#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)

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49#define GPIO_INT_POL_MASK (1 << 1)
50
51struct mxs_gpio_port {
52 void __iomem *base;
53 int id;
54 int irq;
55 int irq_high;
56 int virtual_irq_start;
31#include <mach/mxs.h>
32
33#define MXS_SET 0x4
34#define MXS_CLR 0x8
35
36#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
37#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
38#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)

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50#define GPIO_INT_POL_MASK (1 << 1)
51
52struct mxs_gpio_port {
53 void __iomem *base;
54 int id;
55 int irq;
56 int irq_high;
57 int virtual_irq_start;
57 struct gpio_chip chip;
58 struct bgpio_chip bgc;
58};
59
60/* Note: This driver assumes 32 GPIOs are handled in one register */
61
62static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
63{
64 writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
65}

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94
95static void mxs_gpio_unmask_irq(struct irq_data *d)
96{
97 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
98 u32 gpio = irq_to_gpio(d->irq);
99 set_gpio_irqenable(port, gpio & 0x1f, 1);
100}
101
59};
60
61/* Note: This driver assumes 32 GPIOs are handled in one register */
62
63static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
64{
65 writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
66}

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95
96static void mxs_gpio_unmask_irq(struct irq_data *d)
97{
98 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
99 u32 gpio = irq_to_gpio(d->irq);
100 set_gpio_irqenable(port, gpio & 0x1f, 1);
101}
102
102static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
103
104static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
105{
106 u32 gpio = irq_to_gpio(d->irq);
107 u32 pin_mask = 1 << (gpio & 31);
108 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
109 void __iomem *pin_addr;
110 int edge;
111

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198 .name = "mxs gpio",
199 .irq_ack = mxs_gpio_ack_irq,
200 .irq_mask = mxs_gpio_mask_irq,
201 .irq_unmask = mxs_gpio_unmask_irq,
202 .irq_set_type = mxs_gpio_set_irq_type,
203 .irq_set_wake = mxs_gpio_set_wake_irq,
204};
205
103static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
104{
105 u32 gpio = irq_to_gpio(d->irq);
106 u32 pin_mask = 1 << (gpio & 31);
107 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d);
108 void __iomem *pin_addr;
109 int edge;
110

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197 .name = "mxs gpio",
198 .irq_ack = mxs_gpio_ack_irq,
199 .irq_mask = mxs_gpio_mask_irq,
200 .irq_unmask = mxs_gpio_unmask_irq,
201 .irq_set_type = mxs_gpio_set_irq_type,
202 .irq_set_wake = mxs_gpio_set_wake_irq,
203};
204
206static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
207 int dir)
205static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
208{
206{
207 struct bgpio_chip *bgc = to_bgpio_chip(gc);
209 struct mxs_gpio_port *port =
208 struct mxs_gpio_port *port =
210 container_of(chip, struct mxs_gpio_port, chip);
211 void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
209 container_of(bgc, struct mxs_gpio_port, bgc);
212
210
213 if (dir)
214 writel(1 << offset, pin_addr + MXS_SET);
215 else
216 writel(1 << offset, pin_addr + MXS_CLR);
217}
218
219static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
220{
221 struct mxs_gpio_port *port =
222 container_of(chip, struct mxs_gpio_port, chip);
223
224 return (readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
225}
226
227static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
228{
229 struct mxs_gpio_port *port =
230 container_of(chip, struct mxs_gpio_port, chip);
231 void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
232
233 if (value)
234 writel(1 << offset, pin_addr + MXS_SET);
235 else
236 writel(1 << offset, pin_addr + MXS_CLR);
237}
238
239static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
240{
241 struct mxs_gpio_port *port =
242 container_of(chip, struct mxs_gpio_port, chip);
243
244 return port->virtual_irq_start + offset;
245}
246
211 return port->virtual_irq_start + offset;
212}
213
247static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
248{
249 mxs_set_gpio_direction(chip, offset, 0);
250 return 0;
251}
252
253static int mxs_gpio_direction_output(struct gpio_chip *chip,
254 unsigned offset, int value)
255{
256 mxs_gpio_set(chip, offset, value);
257 mxs_set_gpio_direction(chip, offset, 1);
258 return 0;
259}
260
261static int __devinit mxs_gpio_probe(struct platform_device *pdev)
262{
263 static void __iomem *base;
264 struct mxs_gpio_port *port;
265 struct resource *iores = NULL;
266 int err, i;
267
268 port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);

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317 set_irq_flags(i, IRQF_VALID);
318 irq_set_chip_data(i, port);
319 }
320
321 /* setup one handler for each entry */
322 irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
323 irq_set_handler_data(port->irq, port);
324
214static int __devinit mxs_gpio_probe(struct platform_device *pdev)
215{
216 static void __iomem *base;
217 struct mxs_gpio_port *port;
218 struct resource *iores = NULL;
219 int err, i;
220
221 port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);

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270 set_irq_flags(i, IRQF_VALID);
271 irq_set_chip_data(i, port);
272 }
273
274 /* setup one handler for each entry */
275 irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
276 irq_set_handler_data(port->irq, port);
277
325 /* register gpio chip */
326 port->chip.direction_input = mxs_gpio_direction_input;
327 port->chip.direction_output = mxs_gpio_direction_output;
328 port->chip.get = mxs_gpio_get;
329 port->chip.set = mxs_gpio_set;
330 port->chip.to_irq = mxs_gpio_to_irq;
331 port->chip.base = port->id * 32;
332 port->chip.ngpio = 32;
333
334 err = gpiochip_add(&port->chip);
278 err = bgpio_init(&port->bgc, &pdev->dev, 4,
279 port->base + PINCTRL_DIN(port->id),
280 port->base + PINCTRL_DOUT(port->id), NULL,
281 port->base + PINCTRL_DOE(port->id), NULL, false);
335 if (err)
336 goto out_iounmap;
337
282 if (err)
283 goto out_iounmap;
284
285 port->bgc.gc.to_irq = mxs_gpio_to_irq;
286 port->bgc.gc.base = port->id * 32;
287
288 err = gpiochip_add(&port->bgc.gc);
289 if (err)
290 goto out_bgpio_remove;
291
338 return 0;
339
292 return 0;
293
294out_bgpio_remove:
295 bgpio_remove(&port->bgc);
340out_iounmap:
341 if (iores)
342 iounmap(port->base);
343out_release_mem:
344 if (iores)
345 release_mem_region(iores->start, resource_size(iores));
346out_kfree:
347 kfree(port);

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297 if (iores)
298 iounmap(port->base);
299out_release_mem:
300 if (iores)
301 release_mem_region(iores->start, resource_size(iores));
302out_kfree:
303 kfree(port);

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