gpio-ath79.c (2f890cf0dfe421ecd2095d8cabb89e7207b499ee) gpio-ath79.c (2b8f89e19b6d83d97019358328cbed22bbb0505e)
1/*
2 * Atheros AR71XX/AR724X/AR913X GPIO API support
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include <linux/gpio/driver.h>
16#include <linux/platform_data/gpio-ath79.h>
17#include <linux/of_device.h>
1/*
2 * Atheros AR71XX/AR724X/AR913X GPIO API support
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include <linux/gpio/driver.h>
16#include <linux/platform_data/gpio-ath79.h>
17#include <linux/of_device.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
18
19#define AR71XX_GPIO_REG_OE 0x00
20#define AR71XX_GPIO_REG_IN 0x04
21#define AR71XX_GPIO_REG_SET 0x0c
22#define AR71XX_GPIO_REG_CLEAR 0x10
23
20
21#define AR71XX_GPIO_REG_OE 0x00
22#define AR71XX_GPIO_REG_IN 0x04
23#define AR71XX_GPIO_REG_SET 0x0c
24#define AR71XX_GPIO_REG_CLEAR 0x10
25
26#define AR71XX_GPIO_REG_INT_ENABLE 0x14
27#define AR71XX_GPIO_REG_INT_TYPE 0x18
28#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
29#define AR71XX_GPIO_REG_INT_PENDING 0x20
30#define AR71XX_GPIO_REG_INT_MASK 0x24
31
24struct ath79_gpio_ctrl {
25 struct gpio_chip gc;
26 void __iomem *base;
27 spinlock_t lock;
32struct ath79_gpio_ctrl {
33 struct gpio_chip gc;
34 void __iomem *base;
35 spinlock_t lock;
36 unsigned long both_edges;
28};
29
37};
38
39static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
40{
41 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
42
43 return container_of(gc, struct ath79_gpio_ctrl, gc);
44}
45
46static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
47{
48 return readl(ctrl->base + reg);
49}
50
51static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
52 unsigned reg, u32 val)
53{
54 return writel(val, ctrl->base + reg);
55}
56
57static bool ath79_gpio_update_bits(
58 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
59{
60 u32 old_val, new_val;
61
62 old_val = ath79_gpio_read(ctrl, reg);
63 new_val = (old_val & ~mask) | (bits & mask);
64
65 if (new_val != old_val)
66 ath79_gpio_write(ctrl, reg, new_val);
67
68 return new_val != old_val;
69}
70
71static void ath79_gpio_irq_unmask(struct irq_data *data)
72{
73 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
74 u32 mask = BIT(irqd_to_hwirq(data));
75 unsigned long flags;
76
77 spin_lock_irqsave(&ctrl->lock, flags);
78 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
79 spin_unlock_irqrestore(&ctrl->lock, flags);
80}
81
82static void ath79_gpio_irq_mask(struct irq_data *data)
83{
84 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
85 u32 mask = BIT(irqd_to_hwirq(data));
86 unsigned long flags;
87
88 spin_lock_irqsave(&ctrl->lock, flags);
89 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
90 spin_unlock_irqrestore(&ctrl->lock, flags);
91}
92
93static void ath79_gpio_irq_enable(struct irq_data *data)
94{
95 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
96 u32 mask = BIT(irqd_to_hwirq(data));
97 unsigned long flags;
98
99 spin_lock_irqsave(&ctrl->lock, flags);
100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
101 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
102 spin_unlock_irqrestore(&ctrl->lock, flags);
103}
104
105static void ath79_gpio_irq_disable(struct irq_data *data)
106{
107 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
108 u32 mask = BIT(irqd_to_hwirq(data));
109 unsigned long flags;
110
111 spin_lock_irqsave(&ctrl->lock, flags);
112 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
113 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
114 spin_unlock_irqrestore(&ctrl->lock, flags);
115}
116
117static int ath79_gpio_irq_set_type(struct irq_data *data,
118 unsigned int flow_type)
119{
120 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
121 u32 mask = BIT(irqd_to_hwirq(data));
122 u32 type = 0, polarity = 0;
123 unsigned long flags;
124 bool disabled;
125
126 switch (flow_type) {
127 case IRQ_TYPE_EDGE_RISING:
128 polarity |= mask;
129 case IRQ_TYPE_EDGE_FALLING:
130 case IRQ_TYPE_EDGE_BOTH:
131 break;
132
133 case IRQ_TYPE_LEVEL_HIGH:
134 polarity |= mask;
135 case IRQ_TYPE_LEVEL_LOW:
136 type |= mask;
137 break;
138
139 default:
140 return -EINVAL;
141 }
142
143 spin_lock_irqsave(&ctrl->lock, flags);
144
145 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
146 ctrl->both_edges |= mask;
147 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
148 } else {
149 ctrl->both_edges &= ~mask;
150 }
151
152 /* As the IRQ configuration can't be loaded atomically we
153 * have to disable the interrupt while the configuration state
154 * is invalid.
155 */
156 disabled = ath79_gpio_update_bits(
157 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
158
159 ath79_gpio_update_bits(
160 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
161 ath79_gpio_update_bits(
162 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
163
164 if (disabled)
165 ath79_gpio_update_bits(
166 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
167
168 spin_unlock_irqrestore(&ctrl->lock, flags);
169
170 return 0;
171}
172
173static struct irq_chip ath79_gpio_irqchip = {
174 .name = "gpio-ath79",
175 .irq_enable = ath79_gpio_irq_enable,
176 .irq_disable = ath79_gpio_irq_disable,
177 .irq_mask = ath79_gpio_irq_mask,
178 .irq_unmask = ath79_gpio_irq_unmask,
179 .irq_set_type = ath79_gpio_irq_set_type,
180};
181
182static void ath79_gpio_irq_handler(struct irq_desc *desc)
183{
184 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
185 struct irq_chip *irqchip = irq_desc_get_chip(desc);
186 struct ath79_gpio_ctrl *ctrl =
187 container_of(gc, struct ath79_gpio_ctrl, gc);
188 unsigned long flags, pending;
189 u32 both_edges, state;
190 int irq;
191
192 chained_irq_enter(irqchip, desc);
193
194 spin_lock_irqsave(&ctrl->lock, flags);
195
196 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
197
198 /* Update the polarity of the both edges irqs */
199 both_edges = ctrl->both_edges & pending;
200 if (both_edges) {
201 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
202 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
203 both_edges, ~state);
204 }
205
206 spin_unlock_irqrestore(&ctrl->lock, flags);
207
208 if (pending) {
209 for_each_set_bit(irq, &pending, gc->ngpio)
210 generic_handle_irq(
211 irq_linear_revmap(gc->irqdomain, irq));
212 }
213
214 chained_irq_exit(irqchip, desc);
215}
216
30static const struct of_device_id ath79_gpio_of_match[] = {
31 { .compatible = "qca,ar7100-gpio" },
32 { .compatible = "qca,ar9340-gpio" },
33 {},
34};
35
36static int ath79_gpio_probe(struct platform_device *pdev)
37{

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90
91 err = gpiochip_add_data(&ctrl->gc, ctrl);
92 if (err) {
93 dev_err(&pdev->dev,
94 "cannot add AR71xx GPIO chip, error=%d", err);
95 return err;
96 }
97
217static const struct of_device_id ath79_gpio_of_match[] = {
218 { .compatible = "qca,ar7100-gpio" },
219 { .compatible = "qca,ar9340-gpio" },
220 {},
221};
222
223static int ath79_gpio_probe(struct platform_device *pdev)
224{

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277
278 err = gpiochip_add_data(&ctrl->gc, ctrl);
279 if (err) {
280 dev_err(&pdev->dev,
281 "cannot add AR71xx GPIO chip, error=%d", err);
282 return err;
283 }
284
285 if (np && !of_property_read_bool(np, "interrupt-controller"))
286 return 0;
287
288 err = gpiochip_irqchip_add(&ctrl->gc, &ath79_gpio_irqchip, 0,
289 handle_simple_irq, IRQ_TYPE_NONE);
290 if (err) {
291 dev_err(&pdev->dev, "failed to add gpiochip_irqchip\n");
292 goto gpiochip_remove;
293 }
294
295 gpiochip_set_chained_irqchip(&ctrl->gc, &ath79_gpio_irqchip,
296 platform_get_irq(pdev, 0),
297 ath79_gpio_irq_handler);
298
98 return 0;
299 return 0;
300
301gpiochip_remove:
302 gpiochip_remove(&ctrl->gc);
303 return err;
99}
100
101static int ath79_gpio_remove(struct platform_device *pdev)
102{
103 struct ath79_gpio_ctrl *ctrl = platform_get_drvdata(pdev);
104
105 gpiochip_remove(&ctrl->gc);
106 return 0;

--- 12 unchanged lines hidden --- 		304}
305
306static int ath79_gpio_remove(struct platform_device *pdev)
307{
308 struct ath79_gpio_ctrl *ctrl = platform_get_drvdata(pdev);
309
310 gpiochip_remove(&ctrl->gc);
311 return 0;

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