sysctrl.c (a23e1966932464e1c5226cb9ac4ce1d5fc10ba22) sysctrl.c (9c7a86c935074525f24cc20e78a7d5150e4600e3)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
5 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
6 */
7
8#include <linux/ioport.h>

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242 (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
243 spin_unlock(&g_pmu_lock);
244 }
245
246 if (!retry)
247 pr_warn("deactivating PMU module failed!");
248}
249
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
5 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
6 */
7
8#include <linux/ioport.h>

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242 (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
243 spin_unlock(&g_pmu_lock);
244 }
245
246 if (!retry)
247 pr_warn("deactivating PMU module failed!");
248}
249
250static void usb_set_clock(void)
251{
252 unsigned int val = ltq_cgu_r32(ifccr);
253
254 if (of_machine_is_compatible("lantiq,ar10") ||
255 of_machine_is_compatible("lantiq,grx390")) {
256 val &= ~0x03; /* XTAL divided by 3 */
257 } else if (of_machine_is_compatible("lantiq,ar9") ||
258 of_machine_is_compatible("lantiq,vr9")) {
259 /* TODO: this depends on the XTAL frequency */
260 val |= 0x03; /* XTAL divided by 3 */
261 } else if (of_machine_is_compatible("lantiq,ase")) {
262 val |= 0x20; /* from XTAL */
263 } else if (of_machine_is_compatible("lantiq,danube")) {
264 val |= 0x30; /* 12 MHz, generated from 36 MHz */
265 }
266 ltq_cgu_w32(val, ifccr);
267}
268
250/* the pci enable helper */
251static int pci_enable(struct clk *clk)
252{
253 unsigned int val = ltq_cgu_r32(ifccr);
254 /* set bus clock speed */
255 if (of_machine_is_compatible("lantiq,ar9") ||
256 of_machine_is_compatible("lantiq,vr9")) {
257 val &= ~0x1f00000;

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583 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
584 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
585 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
586 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
587 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
588 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
589 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
590 }
269/* the pci enable helper */
270static int pci_enable(struct clk *clk)
271{
272 unsigned int val = ltq_cgu_r32(ifccr);
273 /* set bus clock speed */
274 if (of_machine_is_compatible("lantiq,ar9") ||
275 of_machine_is_compatible("lantiq,vr9")) {
276 val &= ~0x1f00000;

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602 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
603 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
604 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
605 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
606 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
607 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
608 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
609 }
610 usb_set_clock();
591}
611}