proc-v6.S (f00ec48fadf5e37e7889f14cff900aa70d18b644) proc-v6.S (5085f3ff458521045f7e43da62b8c30ea7df2e82)
1/*
2 * linux/arch/arm/mm/proc-v6.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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25#define TTB_C (1 << 0)
26#define TTB_S (1 << 1)
27#define TTB_IMP (1 << 2)
28#define TTB_RGN_NC (0 << 3)
29#define TTB_RGN_WBWA (1 << 3)
30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3)
32
1/*
2 * linux/arch/arm/mm/proc-v6.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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25#define TTB_C (1 << 0)
26#define TTB_S (1 << 1)
27#define TTB_IMP (1 << 2)
28#define TTB_RGN_NC (0 << 3)
29#define TTB_RGN_WBWA (1 << 3)
30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3)
32
33#define TTB_FLAGS_UP TTB_RGN_WBWA
34#define PMD_FLAGS_UP PMD_SECT_WB
35#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
36#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
33#ifndef CONFIG_SMP
34#define TTB_FLAGS TTB_RGN_WBWA
35#define PMD_FLAGS PMD_SECT_WB
36#else
37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
38#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
39#endif
37
38ENTRY(cpu_v6_proc_init)
39 mov pc, lr
40
41ENTRY(cpu_v6_proc_fin)
42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
43 bic r0, r0, #0x1000 @ ...i............
44 bic r0, r0, #0x0006 @ .............ca.

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89 *
90 * It is assumed that:
91 * - we are not using split page tables
92 */
93ENTRY(cpu_v6_switch_mm)
94#ifdef CONFIG_MMU
95 mov r2, #0
96 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
40
41ENTRY(cpu_v6_proc_init)
42 mov pc, lr
43
44ENTRY(cpu_v6_proc_fin)
45 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 bic r0, r0, #0x1000 @ ...i............
47 bic r0, r0, #0x0006 @ .............ca.

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92 *
93 * It is assumed that:
94 * - we are not using split page tables
95 */
96ENTRY(cpu_v6_switch_mm)
97#ifdef CONFIG_MMU
98 mov r2, #0
99 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
97 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
98 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
100 orr r0, r0, #TTB_FLAGS
99 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
100 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
101 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
102 mcr p15, 0, r1, c13, c0, 1 @ set context ID
103#endif
104 mov pc, lr
105
106/*

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130
131 .type cpu_pj4_name, #object
132cpu_pj4_name:
133 .asciz "Marvell PJ4 processor"
134 .size cpu_pj4_name, . - cpu_pj4_name
135
136 .align
137
101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
103 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
104 mcr p15, 0, r1, c13, c0, 1 @ set context ID
105#endif
106 mov pc, lr
107
108/*

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132
133 .type cpu_pj4_name, #object
134cpu_pj4_name:
135 .asciz "Marvell PJ4 processor"
136 .size cpu_pj4_name, . - cpu_pj4_name
137
138 .align
139
138 __INIT
140 __CPUINIT
139
140/*
141 * __v6_setup
142 *
143 * Initialise TLB, Caches, and MMU state ready to switch the MMU
144 * on. Return in r0 the new CP15 C1 control register setting.
145 *
146 * We automatically detect if we have a Harvard cache, and use the
147 * Harvard cache control instructions insead of the unified cache
148 * control instructions.
149 *
150 * This should be able to cover all ARMv6 cores.
151 *
152 * It is assumed that:
153 * - cache type register is implemented
154 */
155__v6_setup:
156#ifdef CONFIG_SMP
141
142/*
143 * __v6_setup
144 *
145 * Initialise TLB, Caches, and MMU state ready to switch the MMU
146 * on. Return in r0 the new CP15 C1 control register setting.
147 *
148 * We automatically detect if we have a Harvard cache, and use the
149 * Harvard cache control instructions insead of the unified cache
150 * control instructions.
151 *
152 * This should be able to cover all ARMv6 cores.
153 *
154 * It is assumed that:
155 * - cache type register is implemented
156 */
157__v6_setup:
158#ifdef CONFIG_SMP
157 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
158 ALT_UP(nop)
159 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
159 orr r0, r0, #0x20
160 orr r0, r0, #0x20
160 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
161 ALT_UP(nop)
161 mcr p15, 0, r0, c1, c0, 1
162#endif
163
164 mov r0, #0
165 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
166 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
168 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
169#ifdef CONFIG_MMU
170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
162#endif
163
164 mov r0, #0
165 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
166 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
168 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
169#ifdef CONFIG_MMU
170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
172 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
173 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
172 orr r4, r4, #TTB_FLAGS
174 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
175#endif /* CONFIG_MMU */
176 adr r5, v6_crval
177 ldmia r5, {r5, r6}
178#ifdef CONFIG_CPU_ENDIAN_BE8
179 orr r6, r6, #1 << 25 @ big-endian page tables
180#endif
181 mrc p15, 0, r0, c1, c0, 0 @ read control register

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188 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
189 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
190 * 0 110 0011 1.00 .111 1101 < we want
191 */
192 .type v6_crval, #object
193v6_crval:
194 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
195
173 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
174#endif /* CONFIG_MMU */
175 adr r5, v6_crval
176 ldmia r5, {r5, r6}
177#ifdef CONFIG_CPU_ENDIAN_BE8
178 orr r6, r6, #1 << 25 @ big-endian page tables
179#endif
180 mrc p15, 0, r0, c1, c0, 0 @ read control register

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187 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
188 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
189 * 0 110 0011 1.00 .111 1101 < we want
190 */
191 .type v6_crval, #object
192v6_crval:
193 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
194
195 __INITDATA
196
196 .type v6_processor_functions, #object
197ENTRY(v6_processor_functions)
198 .word v6_early_abort
199 .word v6_pabort
200 .word cpu_v6_proc_init
201 .word cpu_v6_proc_fin
202 .word cpu_v6_reset
203 .word cpu_v6_do_idle
204 .word cpu_v6_dcache_clean_area
205 .word cpu_v6_switch_mm
206 .word cpu_v6_set_pte_ext
207 .size v6_processor_functions, . - v6_processor_functions
208
197 .type v6_processor_functions, #object
198ENTRY(v6_processor_functions)
199 .word v6_early_abort
200 .word v6_pabort
201 .word cpu_v6_proc_init
202 .word cpu_v6_proc_fin
203 .word cpu_v6_reset
204 .word cpu_v6_do_idle
205 .word cpu_v6_dcache_clean_area
206 .word cpu_v6_switch_mm
207 .word cpu_v6_set_pte_ext
208 .size v6_processor_functions, . - v6_processor_functions
209
210 .section ".rodata"
211
209 .type cpu_arch_name, #object
210cpu_arch_name:
211 .asciz "armv6"
212 .size cpu_arch_name, . - cpu_arch_name
213
214 .type cpu_elf_name, #object
215cpu_elf_name:
216 .asciz "v6"

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221
222 /*
223 * Match any ARMv6 processor core.
224 */
225 .type __v6_proc_info, #object
226__v6_proc_info:
227 .long 0x0007b000
228 .long 0x0007f000
212 .type cpu_arch_name, #object
213cpu_arch_name:
214 .asciz "armv6"
215 .size cpu_arch_name, . - cpu_arch_name
216
217 .type cpu_elf_name, #object
218cpu_elf_name:
219 .asciz "v6"

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224
225 /*
226 * Match any ARMv6 processor core.
227 */
228 .type __v6_proc_info, #object
229__v6_proc_info:
230 .long 0x0007b000
231 .long 0x0007f000
229 ALT_SMP(.long \
230 PMD_TYPE_SECT | \
232 .long PMD_TYPE_SECT | \
231 PMD_SECT_AP_WRITE | \
232 PMD_SECT_AP_READ | \
233 PMD_SECT_AP_WRITE | \
234 PMD_SECT_AP_READ | \
233 PMD_FLAGS_SMP)
234 ALT_UP(.long \
235 PMD_TYPE_SECT | \
236 PMD_SECT_AP_WRITE | \
237 PMD_SECT_AP_READ | \
238 PMD_FLAGS_UP)
235 PMD_FLAGS
239 .long PMD_TYPE_SECT | \
240 PMD_SECT_XN | \
241 PMD_SECT_AP_WRITE | \
242 PMD_SECT_AP_READ
243 b __v6_setup
244 .long cpu_arch_name
245 .long cpu_elf_name
246 /* See also feat_v6_fixup() for HWCAP_TLS */

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251 .long v6_user_fns
252 .long v6_cache_fns
253 .size __v6_proc_info, . - __v6_proc_info
254
255 .type __pj4_v6_proc_info, #object
256__pj4_v6_proc_info:
257 .long 0x560f5810
258 .long 0xff0ffff0
236 .long PMD_TYPE_SECT | \
237 PMD_SECT_XN | \
238 PMD_SECT_AP_WRITE | \
239 PMD_SECT_AP_READ
240 b __v6_setup
241 .long cpu_arch_name
242 .long cpu_elf_name
243 /* See also feat_v6_fixup() for HWCAP_TLS */

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248 .long v6_user_fns
249 .long v6_cache_fns
250 .size __v6_proc_info, . - __v6_proc_info
251
252 .type __pj4_v6_proc_info, #object
253__pj4_v6_proc_info:
254 .long 0x560f5810
255 .long 0xff0ffff0
259 ALT_SMP(.long \
260 PMD_TYPE_SECT | \
256 .long PMD_TYPE_SECT | \
261 PMD_SECT_AP_WRITE | \
262 PMD_SECT_AP_READ | \
257 PMD_SECT_AP_WRITE | \
258 PMD_SECT_AP_READ | \
263 PMD_FLAGS_SMP)
264 ALT_UP(.long \
265 PMD_TYPE_SECT | \
266 PMD_SECT_AP_WRITE | \
267 PMD_SECT_AP_READ | \
268 PMD_FLAGS_UP)
259 PMD_FLAGS
269 .long PMD_TYPE_SECT | \
270 PMD_SECT_XN | \
271 PMD_SECT_AP_WRITE | \
272 PMD_SECT_AP_READ
273 b __v6_setup
274 .long cpu_arch_name
275 .long cpu_elf_name
276 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
277 .long cpu_pj4_name
278 .long v6_processor_functions
279 .long v6wbi_tlb_fns
280 .long v6_user_fns
281 .long v6_cache_fns
282 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info
260 .long PMD_TYPE_SECT | \
261 PMD_SECT_XN | \
262 PMD_SECT_AP_WRITE | \
263 PMD_SECT_AP_READ
264 b __v6_setup
265 .long cpu_arch_name
266 .long cpu_elf_name
267 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
268 .long cpu_pj4_name
269 .long v6_processor_functions
270 .long v6wbi_tlb_fns
271 .long v6_user_fns
272 .long v6_cache_fns
273 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info