| cache-v7.S (da733563be5a9da26fe81d9f007262d00b846e22) | cache-v7.S (b46c0f74657d1fe1c1b0c1452631cc38a9e6987f) |
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| 1/* 2 * linux/arch/arm/mm/cache-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2005 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 40 unchanged lines hidden (view full) --- 49 beq finished @ if loc is 0, then no need to clean 50 mov r10, #0 @ start clean at cache level 0 51loop1: 52 add r2, r10, r10, lsr #1 @ work out 3x current cache level 53 mov r1, r0, lsr r2 @ extract cache type bits from clidr 54 and r1, r1, #7 @ mask of the bits for current cache only 55 cmp r1, #2 @ see what cache we have at this level 56 blt skip @ skip if no cache, or just i-cache | 1/* 2 * linux/arch/arm/mm/cache-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Copyright (C) 2005 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 40 unchanged lines hidden (view full) --- 49 beq finished @ if loc is 0, then no need to clean 50 mov r10, #0 @ start clean at cache level 0 51loop1: 52 add r2, r10, r10, lsr #1 @ work out 3x current cache level 53 mov r1, r0, lsr r2 @ extract cache type bits from clidr 54 and r1, r1, #7 @ mask of the bits for current cache only 55 cmp r1, #2 @ see what cache we have at this level 56 blt skip @ skip if no cache, or just i-cache |
| 57#ifdef CONFIG_PREEMPT 58 save_and_disable_irqs r9 @ make cssr&csidr read atomic 59#endif |
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| 57 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 58 isb @ isb to sych the new cssr&csidr 59 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | 60 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 61 isb @ isb to sych the new cssr&csidr 62 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr |
| 63#ifdef CONFIG_PREEMPT 64 restore_irqs_notrace r9 65#endif |
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| 60 and r2, r1, #7 @ extract the length of the cache lines 61 add r2, r2, #4 @ add 4 (line length offset) 62 ldr r4, =0x3ff 63 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 64 clz r5, r4 @ find bit position of way size increment 65 ldr r7, =0x7fff 66 ands r7, r7, r1, lsr #13 @ extract max number of the index size 67loop2: --- 282 unchanged lines hidden --- | 66 and r2, r1, #7 @ extract the length of the cache lines 67 add r2, r2, #4 @ add 4 (line length offset) 68 ldr r4, =0x3ff 69 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 70 clz r5, r4 @ find bit position of way size increment 71 ldr r7, =0x7fff 72 ands r7, r7, r1, lsr #13 @ extract max number of the index size 73loop2: --- 282 unchanged lines hidden --- |