| Kconfig (9a38e989b8ce04923f919fc2a8a24eb07fb484e2) | Kconfig (28853ac8fe5221de74a14f1182d7b2b383dfd85c) |
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| 1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction --- 172 unchanged lines hidden (view full) --- 181 help 182 This is a variant of the ARM920. It has slightly different 183 instruction sequences for cache and TLB operations. Curiously, 184 there is no documentation on it at the ARM corporate website. 185 186 Say Y if you want support for the ARM926T processor. 187 Otherwise, say N. 188 | 1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction --- 172 unchanged lines hidden (view full) --- 181 help 182 This is a variant of the ARM920. It has slightly different 183 instruction sequences for cache and TLB operations. Curiously, 184 there is no documentation on it at the ARM corporate website. 185 186 Say Y if you want support for the ARM926T processor. 187 Otherwise, say N. 188 |
| 189# FA526 190config CPU_FA526 191 bool 192 select CPU_32v4 193 select CPU_ABRT_EV4 194 select CPU_PABRT_NOIFAR 195 select CPU_CACHE_VIVT 196 select CPU_CP15_MMU 197 select CPU_CACHE_FA 198 select CPU_COPY_FA if MMU 199 select CPU_TLB_FA if MMU 200 help 201 The FA526 is a version of the ARMv4 compatible processor with 202 Branch Target Buffer, Unified TLB and cache line size 16. 203 204 Say Y if you want support for the FA526 processor. 205 Otherwise, say N. 206 |
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| 189# ARM940T 190config CPU_ARM940T 191 bool "Support ARM940T processor" if ARCH_INTEGRATOR 192 depends on !MMU 193 select CPU_32v4T 194 select CPU_ABRT_NOMMU 195 select CPU_PABRT_NOIFAR 196 select CPU_CACHE_VIVT --- 138 unchanged lines hidden (view full) --- 335 select CPU_32v5 336 select CPU_ABRT_EV5T 337 select CPU_PABRT_NOIFAR 338 select CPU_CACHE_VIVT 339 select CPU_CP15_MMU 340 select CPU_TLB_V4WBI if MMU 341 select IO_36 342 | 207# ARM940T 208config CPU_ARM940T 209 bool "Support ARM940T processor" if ARCH_INTEGRATOR 210 depends on !MMU 211 select CPU_32v4T 212 select CPU_ABRT_NOMMU 213 select CPU_PABRT_NOIFAR 214 select CPU_CACHE_VIVT --- 138 unchanged lines hidden (view full) --- 353 select CPU_32v5 354 select CPU_ABRT_EV5T 355 select CPU_PABRT_NOIFAR 356 select CPU_CACHE_VIVT 357 select CPU_CP15_MMU 358 select CPU_TLB_V4WBI if MMU 359 select IO_36 360 |
| 343# Marvell PJ1 (Mohawk) 344config CPU_MOHAWK 345 bool 346 select CPU_32v5 347 select CPU_ABRT_EV5T 348 select CPU_PABRT_NOIFAR 349 select CPU_CACHE_VIVT 350 select CPU_CP15_MMU 351 select CPU_TLB_V4WBI if MMU 352 select CPU_COPY_V4WB if MMU 353 | |
| 354# Feroceon 355config CPU_FEROCEON 356 bool 357 select CPU_32v5 358 select CPU_ABRT_EV5T 359 select CPU_PABRT_NOIFAR 360 select CPU_CACHE_VIVT 361 select CPU_CP15_MMU --- 128 unchanged lines hidden (view full) --- 490 bool 491 492config CPU_CACHE_VIVT 493 bool 494 495config CPU_CACHE_VIPT 496 bool 497 | 361# Feroceon 362config CPU_FEROCEON 363 bool 364 select CPU_32v5 365 select CPU_ABRT_EV5T 366 select CPU_PABRT_NOIFAR 367 select CPU_CACHE_VIVT 368 select CPU_CP15_MMU --- 128 unchanged lines hidden (view full) --- 497 bool 498 499config CPU_CACHE_VIVT 500 bool 501 502config CPU_CACHE_VIPT 503 bool 504 |
| 505config CPU_CACHE_FA 506 bool 507 |
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| 498if MMU 499# The copy-page model 500config CPU_COPY_V3 501 bool 502 503config CPU_COPY_V4WT 504 bool 505 506config CPU_COPY_V4WB 507 bool 508 509config CPU_COPY_FEROCEON 510 bool 511 | 508if MMU 509# The copy-page model 510config CPU_COPY_V3 511 bool 512 513config CPU_COPY_V4WT 514 bool 515 516config CPU_COPY_V4WB 517 bool 518 519config CPU_COPY_FEROCEON 520 bool 521 |
| 522config CPU_COPY_FA 523 bool 524 |
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| 512config CPU_COPY_V6 513 bool 514 515# This selects the TLB model 516config CPU_TLB_V3 517 bool 518 help 519 ARM Architecture Version 3 TLB. --- 14 unchanged lines hidden (view full) --- 534 ARM Architecture Version 4 TLB with writeback cache and invalidate 535 instruction cache entry. 536 537config CPU_TLB_FEROCEON 538 bool 539 help 540 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 541 | 525config CPU_COPY_V6 526 bool 527 528# This selects the TLB model 529config CPU_TLB_V3 530 bool 531 help 532 ARM Architecture Version 3 TLB. --- 14 unchanged lines hidden (view full) --- 547 ARM Architecture Version 4 TLB with writeback cache and invalidate 548 instruction cache entry. 549 550config CPU_TLB_FEROCEON 551 bool 552 help 553 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 554 |
| 555config CPU_TLB_FA 556 bool 557 help 558 Faraday ARM FA526 architecture, unified TLB with writeback cache 559 and invalidate instruction cache entry. Branch target buffer is 560 also supported. 561 |
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| 542config CPU_TLB_V6 543 bool 544 545config CPU_TLB_V7 546 bool 547 548endif 549 --- 25 unchanged lines hidden (view full) --- 575# 576config IO_36 577 bool 578 579comment "Processor Features" 580 581config ARM_THUMB 582 bool "Support Thumb user binaries" | 562config CPU_TLB_V6 563 bool 564 565config CPU_TLB_V7 566 bool 567 568endif 569 --- 25 unchanged lines hidden (view full) --- 595# 596config IO_36 597 bool 598 599comment "Processor Features" 600 601config ARM_THUMB 602 bool "Support Thumb user binaries" |
| 583 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON | 603 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON |
| 584 default y 585 help 586 Say Y if you want to include kernel support for running user space 587 Thumb binaries. 588 589 The Thumb instruction set is a compressed form of the standard ARM 590 instruction set resulting in smaller binaries at the expense of 591 slightly less efficient code. --- 52 unchanged lines hidden (view full) --- 644 ARM946E-S case, it can vary from 0KB to 1MB. 645 To support such cache operations, it is efficient to know the size 646 before compile time. 647 If your SoC is configured to have a different size, define the value 648 here with proper conditions. 649 650config CPU_DCACHE_WRITETHROUGH 651 bool "Force write through D-cache" | 604 default y 605 help 606 Say Y if you want to include kernel support for running user space 607 Thumb binaries. 608 609 The Thumb instruction set is a compressed form of the standard ARM 610 instruction set resulting in smaller binaries at the expense of 611 slightly less efficient code. --- 52 unchanged lines hidden (view full) --- 664 ARM946E-S case, it can vary from 0KB to 1MB. 665 To support such cache operations, it is efficient to know the size 666 before compile time. 667 If your SoC is configured to have a different size, define the value 668 here with proper conditions. 669 670config CPU_DCACHE_WRITETHROUGH 671 bool "Force write through D-cache" |
| 652 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE | 672 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
| 653 default y if CPU_ARM925T 654 help 655 Say Y here to use the data cache in writethrough mode. Unless you 656 specifically require this or are unsure, say N. 657 658config CPU_CACHE_ROUND_ROBIN 659 bool "Round robin I and D cache replacement algorithm" 660 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 661 help 662 Say Y here to use the predictable round-robin cache replacement 663 policy. Unless you specifically require this or are unsure, say N. 664 665config CPU_BPREDICT_DISABLE 666 bool "Disable branch prediction" | 673 default y if CPU_ARM925T 674 help 675 Say Y here to use the data cache in writethrough mode. Unless you 676 specifically require this or are unsure, say N. 677 678config CPU_CACHE_ROUND_ROBIN 679 bool "Round robin I and D cache replacement algorithm" 680 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 681 help 682 Say Y here to use the predictable round-robin cache replacement 683 policy. Unless you specifically require this or are unsure, say N. 684 685config CPU_BPREDICT_DISABLE 686 bool "Disable branch prediction" |
| 667 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 | 687 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 || CPU_FA526 |
| 668 help 669 Say Y here to disable branch prediction. If unsure, say N. 670 671config TLS_REG_EMUL 672 bool 673 help 674 An SMP system using a pre-ARMv6 processor (there are apparently 675 a few prototypes like that in existence) and therefore access to --- 34 unchanged lines hidden (view full) --- 710 depends on CACHE_FEROCEON_L2 711 default n 712 help 713 Say Y here to use the Feroceon L2 cache in writethrough mode. 714 Unless you specifically require this, say N for writeback mode. 715 716config CACHE_L2X0 717 bool "Enable the L2x0 outer cache controller" | 688 help 689 Say Y here to disable branch prediction. If unsure, say N. 690 691config TLS_REG_EMUL 692 bool 693 help 694 An SMP system using a pre-ARMv6 processor (there are apparently 695 a few prototypes like that in existence) and therefore access to --- 34 unchanged lines hidden (view full) --- 730 depends on CACHE_FEROCEON_L2 731 default n 732 help 733 Say Y here to use the Feroceon L2 cache in writethrough mode. 734 Unless you specifically require this, say N for writeback mode. 735 736config CACHE_L2X0 737 bool "Enable the L2x0 outer cache controller" |
| 718 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 719 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 | 738 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP |
| 720 default y 721 select OUTER_CACHE 722 help 723 This option enables the L2x0 PrimeCell. 724 725config CACHE_XSC3L2 726 bool "Enable the L2 cache on XScale3" 727 depends on CPU_XSC3 728 default y 729 select OUTER_CACHE 730 help 731 This option enables the L2 cache on XScale3. | 739 default y 740 select OUTER_CACHE 741 help 742 This option enables the L2x0 PrimeCell. 743 744config CACHE_XSC3L2 745 bool "Enable the L2 cache on XScale3" 746 depends on CPU_XSC3 747 default y 748 select OUTER_CACHE 749 help 750 This option enables the L2 cache on XScale3. |