| Kconfig (ef70fcc0cd5d98f5e2df82c9e598b47f351d4f66) | Kconfig (70c70d97809c3cdb8ff04f38ee3718c5385a2a4d) |
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| 1# 2# For a description of the syntax of this configuration file, 3# see Documentation/kbuild/kconfig-language.txt. 4# 5 6mainmenu "Linux Kernel Configuration" 7 8config ARM --- 257 unchanged lines hidden (view full) --- 266 select PLAT_VERSATILE 267 help 268 This enables support for the ARM Ltd Versatile Express boards. 269 270config ARCH_AT91 271 bool "Atmel AT91" 272 select ARCH_REQUIRE_GPIOLIB 273 select HAVE_CLK | 1# 2# For a description of the syntax of this configuration file, 3# see Documentation/kbuild/kconfig-language.txt. 4# 5 6mainmenu "Linux Kernel Configuration" 7 8config ARM --- 257 unchanged lines hidden (view full) --- 266 select PLAT_VERSATILE 267 help 268 This enables support for the ARM Ltd Versatile Express boards. 269 270config ARCH_AT91 271 bool "Atmel AT91" 272 select ARCH_REQUIRE_GPIOLIB 273 select HAVE_CLK |
| 274 select ARCH_USES_GETTIMEOFFSET | |
| 275 help 276 This enables support for systems based on the Atmel AT91RM9200, 277 AT91SAM9 and AT91CAP9 processors. 278 279config ARCH_BCMRING 280 bool "Broadcom BCMRING" 281 depends on MMU 282 select CPU_V6 --- 763 unchanged lines hidden (view full) --- 1046 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1047 erratum. Any asynchronous access to the L2 cache may encounter a 1048 situation in which recent store transactions to the L2 cache are lost 1049 and overwritten with stale memory contents from external memory. The 1050 workaround disables the write-allocate mode for the L2 cache via the 1051 ACTLR register. Note that setting specific bits in the ACTLR register 1052 may not be available in non-secure mode. 1053 | 274 help 275 This enables support for systems based on the Atmel AT91RM9200, 276 AT91SAM9 and AT91CAP9 processors. 277 278config ARCH_BCMRING 279 bool "Broadcom BCMRING" 280 depends on MMU 281 select CPU_V6 --- 763 unchanged lines hidden (view full) --- 1045 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1046 erratum. Any asynchronous access to the L2 cache may encounter a 1047 situation in which recent store transactions to the L2 cache are lost 1048 and overwritten with stale memory contents from external memory. The 1049 workaround disables the write-allocate mode for the L2 cache via the 1050 ACTLR register. Note that setting specific bits in the ACTLR register 1051 may not be available in non-secure mode. 1052 |
| 1053config ARM_ERRATA_742230 1054 bool "ARM errata: DMB operation may be faulty" 1055 depends on CPU_V7 && SMP 1056 help 1057 This option enables the workaround for the 742230 Cortex-A9 1058 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1059 between two write operations may not ensure the correct visibility 1060 ordering of the two writes. This workaround sets a specific bit in 1061 the diagnostic register of the Cortex-A9 which causes the DMB 1062 instruction to behave as a DSB, ensuring the correct behaviour of 1063 the two writes. 1064 1065config ARM_ERRATA_742231 1066 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1067 depends on CPU_V7 && SMP 1068 help 1069 This option enables the workaround for the 742231 Cortex-A9 1070 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1071 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1072 accessing some data located in the same cache line, may get corrupted 1073 data due to bad handling of the address hazard when the line gets 1074 replaced from one of the CPUs at the same time as another CPU is 1075 accessing it. This workaround sets specific bits in the diagnostic 1076 register of the Cortex-A9 which reduces the linefill issuing 1077 capabilities of the processor. 1078 |
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| 1054config PL310_ERRATA_588369 1055 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1056 depends on CACHE_L2X0 && ARCH_OMAP4 1057 help 1058 The PL310 L2 cache controller implements three types of Clean & 1059 Invalidate maintenance operations: by Physical Address 1060 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1061 They are architecturally defined to behave as the execution of a --- 371 unchanged lines hidden (view full) --- 1433 1434 A possible side effect is a slight increase in scheduling latency 1435 between threads sharing the same address space if they invoke 1436 such copy operations with large buffers. 1437 1438 However, if the CPU data cache is using a write-allocate mode, 1439 this option is unlikely to provide any performance gain. 1440 | 1079config PL310_ERRATA_588369 1080 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1081 depends on CACHE_L2X0 && ARCH_OMAP4 1082 help 1083 The PL310 L2 cache controller implements three types of Clean & 1084 Invalidate maintenance operations: by Physical Address 1085 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1086 They are architecturally defined to behave as the execution of a --- 371 unchanged lines hidden (view full) --- 1458 1459 A possible side effect is a slight increase in scheduling latency 1460 between threads sharing the same address space if they invoke 1461 such copy operations with large buffers. 1462 1463 However, if the CPU data cache is using a write-allocate mode, 1464 this option is unlikely to provide any performance gain. 1465 |
| 1466config SECCOMP 1467 bool 1468 prompt "Enable seccomp to safely compute untrusted bytecode" 1469 ---help--- 1470 This kernel feature is useful for number crunching applications 1471 that may need to compute untrusted bytecode during their 1472 execution. By using pipes or other transports made available to 1473 the process as file descriptors supporting the read/write 1474 syscalls, it's possible to isolate those applications in 1475 their own address space using seccomp. Once seccomp is 1476 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1477 and the task is only allowed to execute a few safe syscalls 1478 defined by each seccomp mode. 1479 |
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| 1441config CC_STACKPROTECTOR 1442 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1443 help 1444 This option turns on the -fstack-protector GCC feature. This 1445 feature puts, at the beginning of functions, a canary value on 1446 the stack just before the return address, and validates 1447 the value just before actually returning. Stack based buffer 1448 overflows (that need to overwrite this return address) now also --- 323 unchanged lines hidden --- | 1480config CC_STACKPROTECTOR 1481 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1482 help 1483 This option turns on the -fstack-protector GCC feature. This 1484 feature puts, at the beginning of functions, a canary value on 1485 the stack just before the return address, and validates 1486 the value just before actually returning. Stack based buffer 1487 overflows (that need to overwrite this return address) now also --- 323 unchanged lines hidden --- |