| allegro,al5e.yaml (d0034a7a4ac7fae708146ac0059b9c47a1543f0d) | allegro,al5e.yaml (dd3cb467ebb5659d6552999d6f16a616653f9933) |
|---|---|
| 1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/allegro,al5e.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 | 1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/allegro,al5e.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 |
| 7title: Allegro DVT Video IP Codecs Device Tree Bindings | 7title: Allegro DVT Video IP Codecs |
| 8 9maintainers: 10 - Michael Tretter <m.tretter@pengutronix.de> 11 12description: |- 13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may 14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core. 15 --- 90 unchanged lines hidden --- | 8 9maintainers: 10 - Michael Tretter <m.tretter@pengutronix.de> 11 12description: |- 13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may 14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core. 15 --- 90 unchanged lines hidden --- |