sdhci_xenon.c (c80e2ca57e0c1b3647b55471584c6d32214232ea) sdhci_xenon.c (4fa977f854e27c93c22acfa6a3ba38f5c4959e15)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 183 unchanged lines hidden (view full) ---

192static bool
193sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot)
194{
195 struct sdhci_xenon_softc *sc = device_get_softc(dev);
196
197 return (sdhci_fdt_gpio_get_present(sc->gpio));
198}
199
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 183 unchanged lines hidden (view full) ---

192static bool
193sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot)
194{
195 struct sdhci_xenon_softc *sc = device_get_softc(dev);
196
197 return (sdhci_fdt_gpio_get_present(sc->gpio));
198}
199
200static void
201sdhci_xenon_set_uhs_timing(device_t brdev, struct sdhci_slot *slot)
202{
203 const struct mmc_ios *ios;
204 uint16_t hostctrl2;
205
206 if (slot->version < SDHCI_SPEC_300)
207 return;
208
209 mtx_assert(&slot->mtx, MA_OWNED);
210 ios = &slot->host.ios;
211
212 /* Update timing parameteres in SDHCI_HOST_CONTROL2 register. */
213 hostctrl2 = sdhci_xenon_read_2(brdev, slot, SDHCI_HOST_CONTROL2);
214 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK;
215 if (ios->clock > SD_SDR50_MAX) {
216 if (ios->timing == bus_timing_mmc_hs400 ||
217 ios->timing == bus_timing_mmc_hs400es)
218 hostctrl2 |= XENON_CTRL2_MMC_HS400;
219 else if (ios->timing == bus_timing_mmc_hs200)
220 hostctrl2 |= XENON_CTRL2_MMC_HS200;
221 else
222 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104;
223 }
224 else if (ios->clock > SD_SDR25_MAX)
225 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50;
226 else if (ios->clock > SD_SDR12_MAX) {
227 if (ios->timing == bus_timing_uhs_ddr50 ||
228 ios->timing == bus_timing_mmc_ddr52)
229 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50;
230 else
231 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25;
232 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
233 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12;
234 sdhci_xenon_write_2(brdev, slot, SDHCI_HOST_CONTROL2, hostctrl2);
235}
236
200static int
201sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios)
202{
203 int i;
204 struct sdhci_xenon_softc *sc;
205 uint32_t reg;
206
207 sc = device_get_softc(brdev);

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658
659 /* mmcbr_if */
660 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios),
661 DEVMETHOD(mmcbr_request, sdhci_generic_request),
662 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro),
663 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
664 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
665 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq),
237static int
238sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios)
239{
240 int i;
241 struct sdhci_xenon_softc *sc;
242 uint32_t reg;
243
244 sc = device_get_softc(brdev);

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695
696 /* mmcbr_if */
697 DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios),
698 DEVMETHOD(mmcbr_request, sdhci_generic_request),
699 DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro),
700 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
701 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
702 DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq),
703 DEVMETHOD(mmcbr_tune, sdhci_generic_tune),
704 DEVMETHOD(mmcbr_retune, sdhci_generic_retune),
666
667 /* SDHCI registers accessors */
668 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1),
669 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2),
670 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4),
671 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4),
672 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1),
673 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2),
674 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4),
675 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4),
676 DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present),
705
706 /* SDHCI registers accessors */
707 DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1),
708 DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2),
709 DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4),
710 DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4),
711 DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1),
712 DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2),
713 DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4),
714 DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4),
715 DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present),
716 DEVMETHOD(sdhci_set_uhs_timing, sdhci_xenon_set_uhs_timing),
677
678 DEVMETHOD_END
679};
680
681static driver_t sdhci_xenon_driver = {
682 "sdhci_xenon",
683 sdhci_xenon_methods,
684 sizeof(struct sdhci_xenon_softc),
685};
686static devclass_t sdhci_xenon_devclass;
687
688DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass,
689 NULL, NULL);
690
691SDHCI_DEPEND(sdhci_xenon);
692#ifndef MMCCAM
693MMC_DECLARE_BRIDGE(sdhci_xenon);
694#endif
717
718 DEVMETHOD_END
719};
720
721static driver_t sdhci_xenon_driver = {
722 "sdhci_xenon",
723 sdhci_xenon_methods,
724 sizeof(struct sdhci_xenon_softc),
725};
726static devclass_t sdhci_xenon_devclass;
727
728DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass,
729 NULL, NULL);
730
731SDHCI_DEPEND(sdhci_xenon);
732#ifndef MMCCAM
733MMC_DECLARE_BRIDGE(sdhci_xenon);
734#endif