| rtsxreg.h (926ce35a7e33457153b56be1ba51a31aea674000) | rtsxreg.h (577130e56e524eb185ff4d32644dae26be4d28d4) |
|---|---|
| 1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * All rights reserved. 8 * --- 342 unchanged lines hidden (view full) --- 351#define RTSX_SD_RSP_TYPE_R2 0x02 352#define RTSX_SD_RSP_TYPE_R3 0x05 353#define RTSX_SD_RSP_TYPE_R4 0x05 354#define RTSX_SD_RSP_TYPE_R5 0x01 355#define RTSX_SD_RSP_TYPE_R6 0x01 356#define RTSX_SD_RSP_TYPE_R7 0x01 357 358#define RTSX_SD_CFG3 0xFDA2 | 1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * All rights reserved. 8 * --- 342 unchanged lines hidden (view full) --- 351#define RTSX_SD_RSP_TYPE_R2 0x02 352#define RTSX_SD_RSP_TYPE_R3 0x05 353#define RTSX_SD_RSP_TYPE_R4 0x05 354#define RTSX_SD_RSP_TYPE_R5 0x01 355#define RTSX_SD_RSP_TYPE_R6 0x01 356#define RTSX_SD_RSP_TYPE_R7 0x01 357 358#define RTSX_SD_CFG3 0xFDA2 |
| 359#define RTSX_SD30_CLK_END_EN 0x10 |
|
| 359#define RTSX_SD_RSP_80CLK_TIMEOUT_EN 0x01 360 361#define RTSX_SD_STAT1 0xFDA3 362#define RTSX_SD_CRC7_ERR 0x80 363#define RTSX_SD_CRC16_ERR 0x40 364#define RTSX_SD_CRC_WRITE_ERR 0x20 365#define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 366#define RTSX_GET_CRC_TIME_OUT 0x02 --- 105 unchanged lines hidden (view full) --- 472#define RTSX_SD_TRANSFER_ERR 0x10 473 474#define RTSX_SD_CMD_STATE 0xFDB5 475#define RTSX_SD_CMD_IDLE 0x80 476 477#define RTSX_SD_DATA_STATE 0xFDB6 478#define RTSX_SD_DATA_IDLE 0x80 479 | 360#define RTSX_SD_RSP_80CLK_TIMEOUT_EN 0x01 361 362#define RTSX_SD_STAT1 0xFDA3 363#define RTSX_SD_CRC7_ERR 0x80 364#define RTSX_SD_CRC16_ERR 0x40 365#define RTSX_SD_CRC_WRITE_ERR 0x20 366#define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 367#define RTSX_GET_CRC_TIME_OUT 0x02 --- 105 unchanged lines hidden (view full) --- 473#define RTSX_SD_TRANSFER_ERR 0x10 474 475#define RTSX_SD_CMD_STATE 0xFDB5 476#define RTSX_SD_CMD_IDLE 0x80 477 478#define RTSX_SD_DATA_STATE 0xFDB6 479#define RTSX_SD_DATA_IDLE 0x80 480 |
| 481#define RTSX_REG_SD_STOP_SDCLK_CFG 0xFDB8 482#define RTSX_SD30_CLK_STOP_CFG_EN 0x04 483#define RTSX_SD30_CLK_STOP_CFG0 0x01 484#define RTSX_SD30_CLK_STOP_CFG1 0x02 485 486#define RTSX_REG_PRE_RW_MODE 0xFD70 487#define RTSX_EN_INFINITE_MODE 0x01 488 |
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| 480/* ping-pong buffer 2 */ 481#define RTSX_PPBUF_BASE2 0xFA00 482#define RTSX_PPBUF_SIZE 256 483 484#define RTSX_SUPPORTED_VOLTAGE (MMC_OCR_300_310|MMC_OCR_310_320|\ 485 MMC_OCR_320_330|MMC_OCR_330_340) 486 487#define RTSX_CFG_PCI 0x1C --- 26 unchanged lines hidden (view full) --- 514#define RTSX_DMA_128 (0 << 4) 515#define RTSX_DMA_256 (1 << 4) 516#define RTSX_DMA_512 (2 << 4) 517#define RTSX_DMA_1024 (3 << 4) 518#define RTSX_DMA_PACK_SIZE_MASK 0x30 519 520#define RTSX_RBCTL 0xFE34 521#define RTSX_RB_FLUSH 0x80 | 489/* ping-pong buffer 2 */ 490#define RTSX_PPBUF_BASE2 0xFA00 491#define RTSX_PPBUF_SIZE 256 492 493#define RTSX_SUPPORTED_VOLTAGE (MMC_OCR_300_310|MMC_OCR_310_320|\ 494 MMC_OCR_320_330|MMC_OCR_330_340) 495 496#define RTSX_CFG_PCI 0x1C --- 26 unchanged lines hidden (view full) --- 523#define RTSX_DMA_128 (0 << 4) 524#define RTSX_DMA_256 (1 << 4) 525#define RTSX_DMA_512 (2 << 4) 526#define RTSX_DMA_1024 (3 << 4) 527#define RTSX_DMA_PACK_SIZE_MASK 0x30 528 529#define RTSX_RBCTL 0xFE34 530#define RTSX_RB_FLUSH 0x80 |
| 531#define RTSX_U_AUTO_DMA_EN_MASK 0x20 532#define RTSX_U_AUTO_DMA_DISABLE 0x00 |
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| 522 523#define RTSX_CFGADDR0 0xFE35 524#define RTSX_CFGADDR1 0xFE36 525#define RTSX_CFGDATA0 0xFE37 526#define RTSX_CFGDATA1 0xFE38 527#define RTSX_CFGDATA2 0xFE39 528#define RTSX_CFGDATA3 0xFE3A 529#define RTSX_CFGRWCTL 0xFE3B --- 150 unchanged lines hidden (view full) --- 680 681#define RTSX_PME_FORCE_CTL 0xFE56 682 683#define RTSX_ASPM_FORCE_CTL 0xFE57 684#define RTSX_ASPM_FORCE_MASK 0x3F 685#define RTSX_FORCE_ASPM_NO_ASPM 0x00 686 687#define RTSX_PM_CLK_FORCE_CTL 0xFE58 | 533 534#define RTSX_CFGADDR0 0xFE35 535#define RTSX_CFGADDR1 0xFE36 536#define RTSX_CFGDATA0 0xFE37 537#define RTSX_CFGDATA1 0xFE38 538#define RTSX_CFGDATA2 0xFE39 539#define RTSX_CFGDATA3 0xFE3A 540#define RTSX_CFGRWCTL 0xFE3B --- 150 unchanged lines hidden (view full) --- 691 692#define RTSX_PME_FORCE_CTL 0xFE56 693 694#define RTSX_ASPM_FORCE_CTL 0xFE57 695#define RTSX_ASPM_FORCE_MASK 0x3F 696#define RTSX_FORCE_ASPM_NO_ASPM 0x00 697 698#define RTSX_PM_CLK_FORCE_CTL 0xFE58 |
| 699#define RTSX_CLK_PM_EN 0x01 700 |
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| 688#define RTSX_FUNC_FORCE_CTL 0xFE59 689#define RTSX_FUNC_FORCE_UPME_XMT_DBG 0x02 690 691#define RTSX_CHANGE_LINK_STATE 0xFE5B 692#define RTSX_CD_RST_CORE_EN 0x01 693#define RTSX_FORCE_RST_CORE_EN 0x02 694#define RTSX_NON_STICKY_RST_N_DBG 0x08 695#define RTSX_MAC_PHY_RST_N_DBG 0x10 696 697#define RTSX_PERST_GLITCH_WIDTH 0xFE5C 698 699#define RTSX_EFUSE_CONTENT 0xFE5F 700 701#define RTSX_PM_EVENT_DEBUG 0xFE71 702#define RTSX_PME_DEBUG_0 0x08 703 | 701#define RTSX_FUNC_FORCE_CTL 0xFE59 702#define RTSX_FUNC_FORCE_UPME_XMT_DBG 0x02 703 704#define RTSX_CHANGE_LINK_STATE 0xFE5B 705#define RTSX_CD_RST_CORE_EN 0x01 706#define RTSX_FORCE_RST_CORE_EN 0x02 707#define RTSX_NON_STICKY_RST_N_DBG 0x08 708#define RTSX_MAC_PHY_RST_N_DBG 0x10 709 710#define RTSX_PERST_GLITCH_WIDTH 0xFE5C 711 712#define RTSX_EFUSE_CONTENT 0xFE5F 713 714#define RTSX_PM_EVENT_DEBUG 0xFE71 715#define RTSX_PME_DEBUG_0 0x08 716 |
| 717#define RTSX_L1SUB_CONFIG1 0xFE8D 718#define RTSX_AUX_CLK_ACTIVE_SEL_MASK 0x01 719#define RTSX_MAC_CKSW_DONE 0x00 720 |
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| 704#define RTSX_L1SUB_CONFIG2 0xFE8E 705#define RTSX_L1SUB_AUTO_CFG 0x02 706 707#define RTSX_L1SUB_CONFIG3 0xFE8F 708 709#define RTSX_DUMMY_REG 0xFE90 710 | 721#define RTSX_L1SUB_CONFIG2 0xFE8E 722#define RTSX_L1SUB_AUTO_CFG 0x02 723 724#define RTSX_L1SUB_CONFIG3 0xFE8F 725 726#define RTSX_DUMMY_REG 0xFE90 727 |
| 728#define RTSX_RTS5260_DMA_RST_CTL_0 0xFEBF 729#define RTSX_RTS5260_DMA_RST 0x80 730#define RTSX_RTS5260_ADMA3_RST 0x40 731 |
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| 711#define RTSX_PETXCFG 0xFF03 /* was 0xFE49 in OpenBSD */ 712#define RTSX_PETXCFG_CLKREQ_PIN 0x08 713 714#define RTSX_RREF_CFG 0xFF6C 715#define RTSX_RREF_VBGSEL_MASK 0x38 716#define RTSX_RREF_VBGSEL_1V25 0x28 717 718#define RTSX_PM_CTRL3 0xFF46 719#define RTSX_RTS522A_PM_CTRL3 0xFF7E 720#define RTSX_D3_DELINK_MODE_EN 0x10 721#define RTSX_PM_WAKE_EN 0x01 722 723#define RTSX_OOBS_CONFIG 0xFF6E 724#define RTSX_OOBS_AUTOK_DIS 0x80 725#define RTSX_OOBS_VAL_MASK 0x1F 726 | 732#define RTSX_PETXCFG 0xFF03 /* was 0xFE49 in OpenBSD */ 733#define RTSX_PETXCFG_CLKREQ_PIN 0x08 734 735#define RTSX_RREF_CFG 0xFF6C 736#define RTSX_RREF_VBGSEL_MASK 0x38 737#define RTSX_RREF_VBGSEL_1V25 0x28 738 739#define RTSX_PM_CTRL3 0xFF46 740#define RTSX_RTS522A_PM_CTRL3 0xFF7E 741#define RTSX_D3_DELINK_MODE_EN 0x10 742#define RTSX_PM_WAKE_EN 0x01 743 744#define RTSX_OOBS_CONFIG 0xFF6E 745#define RTSX_OOBS_AUTOK_DIS 0x80 746#define RTSX_OOBS_VAL_MASK 0x1F 747 |
| 748#define RTSX_LDO_DV18_CFG 0xFF70 749#define RTSX_DV331812_MASK 0x70 750#define RTSX_DV331812_33 0x70 751 |
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| 727#define RTSX_LDO_CONFIG2 0xFF71 728#define RTSX_LDO_D3318_MASK 0x07 729#define RTSX_LDO_D3318_33V 0x07 730#define RTSX_LDO_D3318_18V 0x02 731#define RTSX_DV331812_VDD1 0x04 732#define RTSX_DV331812_POWERON 0x08 733#define RTSX_DV331812_POWEROFF 0x00 734 735#define RTSX_LDO_VCC_CFG0 0xFF72 736#define RTSX_LDO_VCC_LMTVTH_MASK 0x30 737#define RTSX_LDO_VCC_LMTVTH_2A 0x10 | 752#define RTSX_LDO_CONFIG2 0xFF71 753#define RTSX_LDO_D3318_MASK 0x07 754#define RTSX_LDO_D3318_33V 0x07 755#define RTSX_LDO_D3318_18V 0x02 756#define RTSX_DV331812_VDD1 0x04 757#define RTSX_DV331812_POWERON 0x08 758#define RTSX_DV331812_POWEROFF 0x00 759 760#define RTSX_LDO_VCC_CFG0 0xFF72 761#define RTSX_LDO_VCC_LMTVTH_MASK 0x30 762#define RTSX_LDO_VCC_LMTVTH_2A 0x10 |
| 763#define RTSX_RTS5260_DVCC_TUNE_MASK 0x70 764#define RTSX_RTS5260_DVCC_33 0x70 |
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| 738 739#define RTSX_LDO_VCC_CFG1 0xFF73 740#define RTSX_LDO_VCC_REF_TUNE_MASK 0x30 741#define RTSX_LDO_VCC_REF_1V2 0x20 742#define RTSX_LDO_VCC_TUNE_MASK 0x07 743#define RTSX_LDO_VCC_1V8 0x04 744#define RTSX_LDO_VCC_3V3 0x07 745#define RTSX_LDO_VCC_LMT_EN 0x08 | 765 766#define RTSX_LDO_VCC_CFG1 0xFF73 767#define RTSX_LDO_VCC_REF_TUNE_MASK 0x30 768#define RTSX_LDO_VCC_REF_1V2 0x20 769#define RTSX_LDO_VCC_TUNE_MASK 0x07 770#define RTSX_LDO_VCC_1V8 0x04 771#define RTSX_LDO_VCC_3V3 0x07 772#define RTSX_LDO_VCC_LMT_EN 0x08 |
| 773/*RTS5260*/ 774#define RTSX_LDO_POW_SDVDD1_MASK 0x08 775#define RTSX_LDO_POW_SDVDD1_ON 0x08 776#define RTSX_LDO_POW_SDVDD1_OFF 0x00 |
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| 746 | 777 |
| 778 |
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| 747#define RTSX_LDO_VIO_CFG 0xFF75 748#define RTSX_LDO_VIO_TUNE_MASK 0x07 749#define RTSX_LDO_VIO_1V7 0x03 750 751#define RTSX_LDO_DV12S_CFG 0xFF76 752#define RTSX_LDO_D12_TUNE_MASK 0x07 753#define RTSX_LDO_D12_TUNE_DF 0x04 754 --- 9 unchanged lines hidden (view full) --- 764#define RTSX_SG_TRANS_DATA (0x02 << 4) 765#define RTSX_SG_LINK_DESC (0x03 << 4) 766 767#define RTSX_IC_VERSION_A 0x00 768#define RTSX_IC_VERSION_B 0x01 769#define RTSX_IC_VERSION_C 0x02 770#define RTSX_IC_VERSION_D 0x03 771 | 779#define RTSX_LDO_VIO_CFG 0xFF75 780#define RTSX_LDO_VIO_TUNE_MASK 0x07 781#define RTSX_LDO_VIO_1V7 0x03 782 783#define RTSX_LDO_DV12S_CFG 0xFF76 784#define RTSX_LDO_D12_TUNE_MASK 0x07 785#define RTSX_LDO_D12_TUNE_DF 0x04 786 --- 9 unchanged lines hidden (view full) --- 796#define RTSX_SG_TRANS_DATA (0x02 << 4) 797#define RTSX_SG_LINK_DESC (0x03 << 4) 798 799#define RTSX_IC_VERSION_A 0x00 800#define RTSX_IC_VERSION_B 0x01 801#define RTSX_IC_VERSION_C 0x02 802#define RTSX_IC_VERSION_D 0x03 803 |
| 804#define RTSX_RTS5260_AUTOLOAD_CFG4 0xFF7F 805#define RTSX_RTS5260_MIMO_DISABLE 0x8A 806 |
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| 772#define RTSX_PCR_SETTING_REG1 0x724 773#define RTSX_PCR_SETTING_REG2 0x814 774#define RTSX_PCR_SETTING_REG3 0x747 775 776#define RTSX_RX_PHASE_MAX 32 777#define RTSX_RX_TUNING_CNT 3 778#endif | 807#define RTSX_PCR_SETTING_REG1 0x724 808#define RTSX_PCR_SETTING_REG2 0x814 809#define RTSX_PCR_SETTING_REG3 0x747 810 811#define RTSX_RX_PHASE_MAX 32 812#define RTSX_RX_TUNING_CNT 3 813#endif |