rtsx.c (ad494d3b2d4d46af5d27e2b569ba708adeea7624) rtsx.c (577130e56e524eb185ff4d32644dae26be4d28d4)
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org>
6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be>
7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org>
8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org>

--- 118 unchanged lines hidden (view full) ---

127 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */
128 int32_t rtsx_ios_clock; /* current host.ios.clock */
129 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */
130 int8_t rtsx_ios_timing; /* current host.ios.timing */
131 int8_t rtsx_ios_vccq; /* current host.ios.vccq */
132 uint8_t rtsx_read_only; /* card read only status */
133 uint8_t rtsx_inversion; /* inversion of card detection and read only status */
134 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org>
6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be>
7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org>
8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org>

--- 118 unchanged lines hidden (view full) ---

127 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */
128 int32_t rtsx_ios_clock; /* current host.ios.clock */
129 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */
130 int8_t rtsx_ios_timing; /* current host.ios.timing */
131 int8_t rtsx_ios_vccq; /* current host.ios.vccq */
132 uint8_t rtsx_read_only; /* card read only status */
133 uint8_t rtsx_inversion; /* inversion of card detection and read only status */
134 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */
135 uint8_t rtsx_debug; /* print debugging */
135 uint8_t rtsx_debug_mask; /* debugging mask */
136#define RTSX_DEBUG_BASIC 0x01 /* debug basic flow */
137#define RTSX_TRACE_SD_CMD 0x02 /* trace SD commands */
138#define RTSX_DEBUG_TUNING 0x04 /* debug tuning */
136#ifdef MMCCAM
137 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */
138#endif /* MMCCAM */
139 uint64_t rtsx_read_count; /* count of read operations */
140 uint64_t rtsx_write_count; /* count of write operations */
141 bool rtsx_discovery_mode; /* are we in discovery mode? */
142 bool rtsx_tuning_mode; /* are we tuning */
143 bool rtsx_double_clk; /* double clock freqency */

--- 16 unchanged lines hidden (view full) ---

160
161#define RTSX_REALTEK 0x10ec
162#define RTSX_RTS5209 0x5209
163#define RTSX_RTS5227 0x5227
164#define RTSX_RTS5229 0x5229
165#define RTSX_RTS522A 0x522a
166#define RTSX_RTS525A 0x525a
167#define RTSX_RTS5249 0x5249
139#ifdef MMCCAM
140 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */
141#endif /* MMCCAM */
142 uint64_t rtsx_read_count; /* count of read operations */
143 uint64_t rtsx_write_count; /* count of write operations */
144 bool rtsx_discovery_mode; /* are we in discovery mode? */
145 bool rtsx_tuning_mode; /* are we tuning */
146 bool rtsx_double_clk; /* double clock freqency */

--- 16 unchanged lines hidden (view full) ---

163
164#define RTSX_REALTEK 0x10ec
165#define RTSX_RTS5209 0x5209
166#define RTSX_RTS5227 0x5227
167#define RTSX_RTS5229 0x5229
168#define RTSX_RTS522A 0x522a
169#define RTSX_RTS525A 0x525a
170#define RTSX_RTS5249 0x5249
171#define RTSX_RTS5260 0x5260
168#define RTSX_RTL8402 0x5286
169#define RTSX_RTL8411 0x5289
170#define RTSX_RTL8411B 0x5287
171
172#define RTSX_RTL8402 0x5286
173#define RTSX_RTL8411 0x5289
174#define RTSX_RTL8411B 0x5287
175
172#define RTSX_VERSION "2.1c"
176#define RTSX_VERSION "2.1d"
173
174static const struct rtsx_device {
175 uint16_t vendor_id;
176 uint16_t device_id;
177 const char *desc;
178} rtsx_devices[] = {
179 { RTSX_REALTEK, RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe MMC/SD Card Reader"},
180 { RTSX_REALTEK, RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe MMC/SD Card Reader"},
181 { RTSX_REALTEK, RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe MMC/SD Card Reader"},
182 { RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe MMC/SD Card Reader"},
183 { RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe MMC/SD Card Reader"},
184 { RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe MMC/SD Card Reader"},
177
178static const struct rtsx_device {
179 uint16_t vendor_id;
180 uint16_t device_id;
181 const char *desc;
182} rtsx_devices[] = {
183 { RTSX_REALTEK, RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe MMC/SD Card Reader"},
184 { RTSX_REALTEK, RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe MMC/SD Card Reader"},
185 { RTSX_REALTEK, RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe MMC/SD Card Reader"},
186 { RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe MMC/SD Card Reader"},
187 { RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe MMC/SD Card Reader"},
188 { RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe MMC/SD Card Reader"},
189 { RTSX_REALTEK, RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe MMC/SD Card Reader"},
185 { RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe MMC/SD Card Reader"},
186 { RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe MMC/SD Card Reader"},
187 { RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe MMC/SD Card Reader"},
188 { 0, 0, NULL}
189};
190
191/* See `kenv | grep smbios.system` */
192static const struct rtsx_inversion_model {

--- 11 unchanged lines hidden (view full) ---

204static void rtsx_intr(void *arg);
205static void rtsx_handle_card_present(struct rtsx_softc *sc);
206static void rtsx_card_task(void *arg, int pending __unused);
207static bool rtsx_is_card_present(struct rtsx_softc *sc);
208static int rtsx_init(struct rtsx_softc *sc);
209static int rtsx_map_sd_drive(int index);
210static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc);
211static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc);
190 { RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe MMC/SD Card Reader"},
191 { RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe MMC/SD Card Reader"},
192 { RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe MMC/SD Card Reader"},
193 { 0, 0, NULL}
194};
195
196/* See `kenv | grep smbios.system` */
197static const struct rtsx_inversion_model {

--- 11 unchanged lines hidden (view full) ---

209static void rtsx_intr(void *arg);
210static void rtsx_handle_card_present(struct rtsx_softc *sc);
211static void rtsx_card_task(void *arg, int pending __unused);
212static bool rtsx_is_card_present(struct rtsx_softc *sc);
213static int rtsx_init(struct rtsx_softc *sc);
214static int rtsx_map_sd_drive(int index);
215static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc);
216static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc);
217static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc);
212static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *);
213static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val);
214static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val);
215static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val);
216static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val);
217static int rtsx_bus_power_off(struct rtsx_softc *sc);
218static int rtsx_bus_power_on(struct rtsx_softc *sc);
219static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width);

--- 330 unchanged lines hidden (view full) ---

550 uint32_t status;
551
552 RTSX_LOCK(sc);
553
554 enabled = sc->rtsx_intr_enabled;
555 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */
556 sc->rtsx_intr_status = status;
557
218static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *);
219static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val);
220static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val);
221static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val);
222static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val);
223static int rtsx_bus_power_off(struct rtsx_softc *sc);
224static int rtsx_bus_power_on(struct rtsx_softc *sc);
225static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width);

--- 330 unchanged lines hidden (view full) ---

556 uint32_t status;
557
558 RTSX_LOCK(sc);
559
560 enabled = sc->rtsx_intr_enabled;
561 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */
562 sc->rtsx_intr_status = status;
563
558 if (bootverbose)
564 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
559 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status);
560
561 /* Ack interrupts. */
562 WRITE4(sc, RTSX_BIPR, status);
563
564 if (((enabled & status) == 0) || status == 0xffffffff) {
565 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status);
566 RTSX_UNLOCK(sc);

--- 83 unchanged lines hidden (view full) ---

650 if (rtsx_is_card_present(sc)) {
651 sc->rtsx_flags |= RTSX_F_CARD_PRESENT;
652 /* Card is present, attach if necessary. */
653#ifdef MMCCAM
654 if (sc->rtsx_cam_status == 0) {
655#else /* !MMCCAM */
656 if (sc->rtsx_mmc_dev == NULL) {
657#endif /* MMCCAM */
565 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status);
566
567 /* Ack interrupts. */
568 WRITE4(sc, RTSX_BIPR, status);
569
570 if (((enabled & status) == 0) || status == 0xffffffff) {
571 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status);
572 RTSX_UNLOCK(sc);

--- 83 unchanged lines hidden (view full) ---

656 if (rtsx_is_card_present(sc)) {
657 sc->rtsx_flags |= RTSX_F_CARD_PRESENT;
658 /* Card is present, attach if necessary. */
659#ifdef MMCCAM
660 if (sc->rtsx_cam_status == 0) {
661#else /* !MMCCAM */
662 if (sc->rtsx_mmc_dev == NULL) {
663#endif /* MMCCAM */
658 if (bootverbose)
664 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
659 device_printf(sc->rtsx_dev, "Card inserted\n");
660
661 sc->rtsx_read_count = sc->rtsx_write_count = 0;
662#ifdef MMCCAM
663 sc->rtsx_cam_status = 1;
664 mmc_cam_sim_discover(&sc->rtsx_mmc_sim);
665#else /* !MMCCAM */
666 RTSX_LOCK(sc);

--- 10 unchanged lines hidden (view full) ---

677 } else {
678 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT;
679 /* Card isn't present, detach if necessary. */
680#ifdef MMCCAM
681 if (sc->rtsx_cam_status != 0) {
682#else /* !MMCCAM */
683 if (sc->rtsx_mmc_dev != NULL) {
684#endif /* MMCCAM */
665 device_printf(sc->rtsx_dev, "Card inserted\n");
666
667 sc->rtsx_read_count = sc->rtsx_write_count = 0;
668#ifdef MMCCAM
669 sc->rtsx_cam_status = 1;
670 mmc_cam_sim_discover(&sc->rtsx_mmc_sim);
671#else /* !MMCCAM */
672 RTSX_LOCK(sc);

--- 10 unchanged lines hidden (view full) ---

683 } else {
684 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT;
685 /* Card isn't present, detach if necessary. */
686#ifdef MMCCAM
687 if (sc->rtsx_cam_status != 0) {
688#else /* !MMCCAM */
689 if (sc->rtsx_mmc_dev != NULL) {
690#endif /* MMCCAM */
685 if (bootverbose)
691 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
686 device_printf(sc->rtsx_dev, "Card removed\n");
687
692 device_printf(sc->rtsx_dev, "Card removed\n");
693
688 if (sc->rtsx_debug)
694 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
689 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n",
690 sc->rtsx_read_count, sc->rtsx_write_count);
691#ifdef MMCCAM
692 sc->rtsx_cam_status = 0;
693 mmc_cam_sim_discover(&sc->rtsx_mmc_sim);
694#else /* !MMCCAM */
695 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev))
696 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n");

--- 13 unchanged lines hidden (view full) ---

710 return (status & RTSX_SD_EXIST);
711 else
712 return !(status & RTSX_SD_EXIST);
713}
714
715static int
716rtsx_init(struct rtsx_softc *sc)
717{
695 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n",
696 sc->rtsx_read_count, sc->rtsx_write_count);
697#ifdef MMCCAM
698 sc->rtsx_cam_status = 0;
699 mmc_cam_sim_discover(&sc->rtsx_mmc_sim);
700#else /* !MMCCAM */
701 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev))
702 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n");

--- 13 unchanged lines hidden (view full) ---

716 return (status & RTSX_SD_EXIST);
717 else
718 return !(status & RTSX_SD_EXIST);
719}
720
721static int
722rtsx_init(struct rtsx_softc *sc)
723{
718 bool rtsx_init_debug = false;
719 uint8_t version;
720 uint8_t val;
721 int error;
722
723 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE;
724 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ;
725 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ;
726 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED |

--- 49 unchanged lines hidden (view full) ---

776 uint8_t reg3;
777 case RTSX_RTS5209:
778 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT;
779 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
780 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
781 if (!(reg & 0x80)) {
782 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F;
783 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07;
724 uint8_t version;
725 uint8_t val;
726 int error;
727
728 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE;
729 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ;
730 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ;
731 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED |

--- 49 unchanged lines hidden (view full) ---

781 uint8_t reg3;
782 case RTSX_RTS5209:
783 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT;
784 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
785 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
786 if (!(reg & 0x80)) {
787 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F;
788 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07;
784 } else if (bootverbose || rtsx_init_debug) {
789 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
785 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
786 }
790 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
791 }
787 if (bootverbose || rtsx_init_debug)
792 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
788 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
789 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
790 break;
791 case RTSX_RTS5227:
792 case RTSX_RTS522A:
793 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B;
794 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
795 if (!(reg & 0x1000000)) {
796 sc->rtsx_card_drive_sel &= 0x3F;
797 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
798 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
799 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
800 if (reg & 0x4000)
801 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
793 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
794 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
795 break;
796 case RTSX_RTS5227:
797 case RTSX_RTS522A:
798 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B;
799 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
800 if (!(reg & 0x1000000)) {
801 sc->rtsx_card_drive_sel &= 0x3F;
802 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
803 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
804 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
805 if (reg & 0x4000)
806 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
802 } else if (bootverbose || rtsx_init_debug) {
807 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
803 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
804 }
808 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
809 }
805 if (bootverbose || rtsx_init_debug)
810 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
806 device_printf(sc->rtsx_dev,
807 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n",
808 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
809 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false");
810 break;
811 case RTSX_RTS5229:
812 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
813 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
814 if (!(reg & 0x1000000)) {
815 sc->rtsx_card_drive_sel &= 0x3F;
816 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
817 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
818 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03);
811 device_printf(sc->rtsx_dev,
812 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n",
813 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
814 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false");
815 break;
816 case RTSX_RTS5229:
817 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
818 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
819 if (!(reg & 0x1000000)) {
820 sc->rtsx_card_drive_sel &= 0x3F;
821 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
822 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
823 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03);
819 } else if (bootverbose || rtsx_init_debug) {
824 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
820 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
821 }
825 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
826 }
822 if (bootverbose || rtsx_init_debug)
827 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
823 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
824 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
825 break;
826 case RTSX_RTS525A:
827 case RTSX_RTS5249:
828 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
829 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
830 break;
831 case RTSX_RTS525A:
832 case RTSX_RTS5249:
833 case RTSX_RTS5260:
828 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B;
829 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
830 if ((reg & 0x1000000)) {
831 sc->rtsx_card_drive_sel &= 0x3F;
832 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
833 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
834 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
835 if (reg & 0x4000)
836 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
834 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B;
835 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
836 if ((reg & 0x1000000)) {
837 sc->rtsx_card_drive_sel &= 0x3F;
838 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6;
839 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4);
840 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03;
841 if (reg & 0x4000)
842 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET;
837 } else if (bootverbose || rtsx_init_debug) {
843 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
838 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
839 }
844 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
845 }
840 if (bootverbose || rtsx_init_debug)
846 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
841 device_printf(sc->rtsx_dev,
842 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n",
843 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
844 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false");
845 break;
846 case RTSX_RTL8402:
847 case RTSX_RTL8411:
848 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT;
849 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
850 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
851 if (reg1 & 0x1000000) {
852 sc->rtsx_card_drive_sel &= 0x3F;
853 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6;
854 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1);
855 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07;
847 device_printf(sc->rtsx_dev,
848 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n",
849 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3,
850 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false");
851 break;
852 case RTSX_RTL8402:
853 case RTSX_RTL8411:
854 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT;
855 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
856 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
857 if (reg1 & 0x1000000) {
858 sc->rtsx_card_drive_sel &= 0x3F;
859 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6;
860 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1);
861 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07;
856 } else if (bootverbose || rtsx_init_debug) {
862 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
857 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1);
858 }
863 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1);
864 }
859 if (bootverbose || rtsx_init_debug)
865 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
860 device_printf(sc->rtsx_dev,
861 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
862 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
863 break;
864 case RTSX_RTL8411B:
865 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT;
866 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
867 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
868 if (!(reg & 0x1000000)) {
869 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03);
866 device_printf(sc->rtsx_dev,
867 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
868 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
869 break;
870 case RTSX_RTL8411B:
871 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT;
872 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D;
873 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4);
874 if (!(reg & 0x1000000)) {
875 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03);
870 } else if (bootverbose || rtsx_init_debug) {
876 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
871 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
872 }
877 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg);
878 }
873 if (bootverbose || rtsx_init_debug)
879 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
874 device_printf(sc->rtsx_dev,
875 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
876 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
877 break;
878 }
879
880 device_printf(sc->rtsx_dev,
881 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n",
882 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3);
883 break;
884 }
885
880 if (bootverbose || rtsx_init_debug)
886 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
881 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags);
882
883 /* Enable interrupts. */
884 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN | RTSX_MS_INT_EN;
885 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled);
886
887 /* Power on SSC clock. */
888 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN);

--- 305 unchanged lines hidden (view full) ---

1194 if ((error = rtsx_rts5249_fill_driving(sc)))
1195 return (error);
1196 /* Configure force_clock_req. */
1197 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1198 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
1199 else
1200 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
1201 break;
887 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags);
888
889 /* Enable interrupts. */
890 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN | RTSX_MS_INT_EN;
891 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled);
892
893 /* Power on SSC clock. */
894 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN);

--- 305 unchanged lines hidden (view full) ---

1200 if ((error = rtsx_rts5249_fill_driving(sc)))
1201 return (error);
1202 /* Configure force_clock_req. */
1203 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1204 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
1205 else
1206 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
1207 break;
1208 case RTSX_RTS5260:
1209 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */
1210 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07);
1211 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D);
1212 /* force no MDIO*/
1213 RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE);
1214 /*Modify SDVCC Tune Default Parameters!*/
1215 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33);
1216 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL);
1217 RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE);
1218 /* Rest L1SUB Config */
1219 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF);
1220 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN);
1221 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN);
1222 RTSX_BITOP(sc, RTSX_RB_FLUSH, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE);
1223 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET)
1224 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0);
1225 else
1226 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80);
1227 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE);
1228 break;
1202 case RTSX_RTL8402:
1203 case RTSX_RTL8411:
1204 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3);
1205 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE,
1206 RTSX_CD_ENABLE);
1207 break;
1208 case RTSX_RTL8411B:
1209 if (sc->rtsx_flags & RTSX_F_8411B_QFN48)

--- 59 unchanged lines hidden (view full) ---

1269 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]);
1270 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]);
1271 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]);
1272
1273 return (0);
1274}
1275
1276static int
1229 case RTSX_RTL8402:
1230 case RTSX_RTL8411:
1231 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3);
1232 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE,
1233 RTSX_CD_ENABLE);
1234 break;
1235 case RTSX_RTL8411B:
1236 if (sc->rtsx_flags & RTSX_F_8411B_QFN48)

--- 59 unchanged lines hidden (view full) ---

1296 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]);
1297 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]);
1298 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]);
1299
1300 return (0);
1301}
1302
1303static int
1304rtsx_rts5260_fill_driving(struct rtsx_softc *sc)
1305{
1306 u_char driving_3v3[4][3] = {
1307 {0x11, 0x11, 0x11},
1308 {0x22, 0x22, 0x22},
1309 {0x55, 0x55, 0x55},
1310 {0x33, 0x33, 0x33},
1311 };
1312 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]);
1313 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]);
1314 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]);
1315
1316 return (0);
1317}
1318
1319static int
1277rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val)
1278{
1279 int tries = 1024;
1280 uint32_t reg;
1281
1282 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY |
1283 (uint32_t)((addr & 0x3FFF) << 16));
1284

--- 106 unchanged lines hidden (view full) ---

1391/*
1392 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and
1393 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229
1394 * it is a mask of *enabled* gates.
1395 */
1396static int
1397rtsx_bus_power_off(struct rtsx_softc *sc)
1398{
1320rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val)
1321{
1322 int tries = 1024;
1323 uint32_t reg;
1324
1325 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY |
1326 (uint32_t)((addr & 0x3FFF) << 16));
1327

--- 106 unchanged lines hidden (view full) ---

1434/*
1435 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and
1436 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229
1437 * it is a mask of *enabled* gates.
1438 */
1439static int
1440rtsx_bus_power_off(struct rtsx_softc *sc)
1441{
1399 if (bootverbose || sc->rtsx_debug)
1442 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1400 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n");
1401
1402 /* Disable SD clock. */
1403 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN);
1404
1405 /* Disable SD output. */
1406 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN);
1407

--- 6 unchanged lines hidden (view full) ---

1414 break;
1415 case RTSX_RTS5227:
1416 case RTSX_RTS5229:
1417 case RTSX_RTS522A:
1418 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK,
1419 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA);
1420 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK);
1421 break;
1443 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n");
1444
1445 /* Disable SD clock. */
1446 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN);
1447
1448 /* Disable SD output. */
1449 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN);
1450

--- 6 unchanged lines hidden (view full) ---

1457 break;
1458 case RTSX_RTS5227:
1459 case RTSX_RTS5229:
1460 case RTSX_RTS522A:
1461 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK,
1462 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA);
1463 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK);
1464 break;
1465 case RTSX_RTS5260:
1466 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF);
1467 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF);
1468 break;
1422 case RTSX_RTL8402:
1423 case RTSX_RTL8411:
1424 case RTSX_RTL8411B:
1425 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1426 RTSX_BPP_POWER_OFF);
1427 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
1428 RTSX_BPP_LDO_SUSPEND);
1429 break;

--- 20 unchanged lines hidden (view full) ---

1450 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1451 if (sc->rtsx_flags & RTSX_F_VERSION_C)
1452 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C);
1453 else
1454 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1455 break;
1456 case RTSX_RTS525A:
1457 case RTSX_RTS5249:
1469 case RTSX_RTL8402:
1470 case RTSX_RTL8411:
1471 case RTSX_RTL8411B:
1472 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1473 RTSX_BPP_POWER_OFF);
1474 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
1475 RTSX_BPP_LDO_SUSPEND);
1476 break;

--- 20 unchanged lines hidden (view full) ---

1497 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1498 if (sc->rtsx_flags & RTSX_F_VERSION_C)
1499 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C);
1500 else
1501 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1502 break;
1503 case RTSX_RTS525A:
1504 case RTSX_RTS5249:
1505 case RTSX_RTS5260:
1458 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
1459 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1460 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1461 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55);
1462 break;
1463 case RTSX_RTL8402:
1464 case RTSX_RTL8411:
1465 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65);

--- 20 unchanged lines hidden (view full) ---

1486 }
1487
1488 return (0);
1489}
1490
1491static int
1492rtsx_bus_power_on(struct rtsx_softc *sc)
1493{
1506 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
1507 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
1508 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3);
1509 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55);
1510 break;
1511 case RTSX_RTL8402:
1512 case RTSX_RTL8411:
1513 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65);

--- 20 unchanged lines hidden (view full) ---

1534 }
1535
1536 return (0);
1537}
1538
1539static int
1540rtsx_bus_power_on(struct rtsx_softc *sc)
1541{
1494 if (bootverbose || sc->rtsx_debug)
1542 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1495 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n");
1496
1497 /* Select SD card. */
1498 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL);
1499 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD);
1500
1501 /* Enable SD clock. */
1502 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN);

--- 14 unchanged lines hidden (view full) ---

1517 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1518 if (sc->rtsx_flags & RTSX_F_VERSION_C)
1519 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C);
1520 else
1521 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1522 break;
1523 case RTSX_RTS525A:
1524 case RTSX_RTS5249:
1543 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n");
1544
1545 /* Select SD card. */
1546 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL);
1547 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD);
1548
1549 /* Enable SD clock. */
1550 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN);

--- 14 unchanged lines hidden (view full) ---

1565 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1566 if (sc->rtsx_flags & RTSX_F_VERSION_C)
1567 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C);
1568 else
1569 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1570 break;
1571 case RTSX_RTS525A:
1572 case RTSX_RTS5249:
1573 case RTSX_RTS5260:
1525 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
1526 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1527 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1528 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa);
1529 break;
1530 case RTSX_RTL8402:
1531 case RTSX_RTL8411:
1532 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa);

--- 71 unchanged lines hidden (view full) ---

1604
1605 DELAY(5000);
1606
1607 /* Full power. */
1608 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON);
1609 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK,
1610 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2);
1611 break;
1574 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66);
1575 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
1576 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3);
1577 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa);
1578 break;
1579 case RTSX_RTL8402:
1580 case RTSX_RTL8411:
1581 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa);

--- 71 unchanged lines hidden (view full) ---

1653
1654 DELAY(5000);
1655
1656 /* Full power. */
1657 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON);
1658 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK,
1659 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2);
1660 break;
1661 case RTSX_RTS5260:
1662 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
1663 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33);
1664 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON);
1665 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON);
1666
1667 DELAY(20000);
1668
1669 /* Initialize SD_CFG1 register */
1670 RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE);
1671 RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE);
1672 RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff);
1673 RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_MS_STOP | RTSX_SD_CLR_ERR,
1674 RTSX_MS_STOP | RTSX_SD_CLR_ERR);
1675 /* Reset SD_CFG3 register */
1676 RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN);
1677 RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG,
1678 RTSX_SD30_CLK_STOP_CFG_EN | RTSX_SD30_CLK_STOP_CFG0 | RTSX_SD30_CLK_STOP_CFG1);
1679 RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE);
1680 break;
1612 case RTSX_RTL8402:
1613 case RTSX_RTL8411:
1614 case RTSX_RTL8411B:
1615 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1616 RTSX_BPP_POWER_5_PERCENT_ON);
1617 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
1618 RTSX_BPP_LDO_SUSPEND);
1619 DELAY(150);

--- 36 unchanged lines hidden (view full) ---

1656 case bus_width_8:
1657 bus_width = RTSX_BUS_WIDTH_8;
1658 break;
1659 default:
1660 return (MMC_ERR_INVALID);
1661 }
1662 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width);
1663
1681 case RTSX_RTL8402:
1682 case RTSX_RTL8411:
1683 case RTSX_RTL8411B:
1684 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
1685 RTSX_BPP_POWER_5_PERCENT_ON);
1686 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
1687 RTSX_BPP_LDO_SUSPEND);
1688 DELAY(150);

--- 36 unchanged lines hidden (view full) ---

1725 case bus_width_8:
1726 bus_width = RTSX_BUS_WIDTH_8;
1727 break;
1728 default:
1729 return (MMC_ERR_INVALID);
1730 }
1731 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width);
1732
1664 if (bootverbose || sc->rtsx_debug) {
1733 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
1665 char *busw[] = {
1666 "1 bit",
1667 "4 bits",
1668 "8 bits"
1669 };
1670 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]);
1671 }
1672 return (0);
1673}
1674
1675static int
1676rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing)
1677{
1678 if (timing == bus_timing_hs && sc->rtsx_force_timing) {
1679 timing = bus_timing_uhs_sdr50;
1680 sc->rtsx_ios_timing = timing;
1681 }
1682
1734 char *busw[] = {
1735 "1 bit",
1736 "4 bits",
1737 "8 bits"
1738 };
1739 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]);
1740 }
1741 return (0);
1742}
1743
1744static int
1745rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing)
1746{
1747 if (timing == bus_timing_hs && sc->rtsx_force_timing) {
1748 timing = bus_timing_uhs_sdr50;
1749 sc->rtsx_ios_timing = timing;
1750 }
1751
1683 if (bootverbose || sc->rtsx_debug)
1752 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1684 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing);
1685
1686 switch (timing) {
1687 case bus_timing_uhs_sdr50:
1688 case bus_timing_uhs_sdr104:
1689 sc->rtsx_double_clk = false;
1690 sc->rtsx_vpclk = true;
1691 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST,

--- 37 unchanged lines hidden (view full) ---

1729 */
1730static int
1731rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq)
1732{
1733 uint8_t clk;
1734 uint8_t clk_divider, n, div, mcu;
1735 int error = 0;
1736
1753 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing);
1754
1755 switch (timing) {
1756 case bus_timing_uhs_sdr50:
1757 case bus_timing_uhs_sdr104:
1758 sc->rtsx_double_clk = false;
1759 sc->rtsx_vpclk = true;
1760 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST,

--- 37 unchanged lines hidden (view full) ---

1798 */
1799static int
1800rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq)
1801{
1802 uint8_t clk;
1803 uint8_t clk_divider, n, div, mcu;
1804 int error = 0;
1805
1737 if (bootverbose || sc->rtsx_debug)
1806 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1738 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq);
1739
1740 if (freq == RTSX_SDCLK_OFF) {
1741 error = rtsx_stop_sd_clock(sc);
1742 return error;
1743 }
1744
1745 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K;

--- 70 unchanged lines hidden (view full) ---

1816 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP);
1817
1818 return (0);
1819}
1820
1821static int
1822rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu)
1823{
1807 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq);
1808
1809 if (freq == RTSX_SDCLK_OFF) {
1810 error = rtsx_stop_sd_clock(sc);
1811 return error;
1812 }
1813
1814 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K;

--- 70 unchanged lines hidden (view full) ---

1885 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP);
1886
1887 return (0);
1888}
1889
1890static int
1891rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu)
1892{
1824 if (bootverbose || sc->rtsx_debug) {
1893 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) {
1825 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n",
1826 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth);
1827 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n",
1828 clk, n, div, mcu);
1829 }
1830
1831 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ);
1832 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu);

--- 13 unchanged lines hidden (view full) ---

1846
1847 return (0);
1848}
1849
1850#ifndef MMCCAM
1851static void
1852rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point)
1853{
1894 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n",
1895 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth);
1896 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n",
1897 clk, n, div, mcu);
1898 }
1899
1900 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ);
1901 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu);

--- 13 unchanged lines hidden (view full) ---

1915
1916 return (0);
1917}
1918
1919#ifndef MMCCAM
1920static void
1921rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point)
1922{
1854 if (bootverbose || sc->rtsx_debug)
1923 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
1855 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point);
1856
1857 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
1858 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point);
1859 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0);
1860 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET);
1861 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0);
1862 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0);
1863}
1864
1865static void
1866rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point)
1867{
1924 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point);
1925
1926 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
1927 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point);
1928 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0);
1929 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET);
1930 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0);
1931 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0);
1932}
1933
1934static void
1935rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point)
1936{
1868 if (bootverbose || sc->rtsx_debug == 2)
1937 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING)
1869 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point);
1870
1871 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
1872 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point);
1873 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0);
1874 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET);
1875 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0);
1876 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0);

--- 50 unchanged lines hidden (view full) ---

1927 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup;
1928
1929 /* Run the command queue. */
1930 rtsx_send_cmd(sc);
1931
1932 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd);
1933
1934 if (error) {
1938 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point);
1939
1940 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK);
1941 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point);
1942 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0);
1943 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET);
1944 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0);
1945 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0);

--- 50 unchanged lines hidden (view full) ---

1996 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup;
1997
1998 /* Run the command queue. */
1999 rtsx_send_cmd(sc);
2000
2001 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd);
2002
2003 if (error) {
1935 if (bootverbose || sc->rtsx_debug == 2)
2004 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING)
1936 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error);
1937 rtsx_sd_wait_data_idle(sc);
1938 rtsx_clear_error(sc);
1939 }
1940 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0);
1941
1942 sc->rtsx_req = NULL;
1943

--- 52 unchanged lines hidden (view full) ---

1996 start_final = start;
1997 len_final = len;
1998 }
1999 start += len ? len : 1;
2000 }
2001
2002 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX;
2003
2005 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error);
2006 rtsx_sd_wait_data_idle(sc);
2007 rtsx_clear_error(sc);
2008 }
2009 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0);
2010
2011 sc->rtsx_req = NULL;
2012

--- 52 unchanged lines hidden (view full) ---

2065 start_final = start;
2066 len_final = len;
2067 }
2068 start += len ? len : 1;
2069 }
2070
2071 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX;
2072
2004 if (bootverbose || sc->rtsx_debug)
2073 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2005 device_printf(sc->rtsx_dev,
2006 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n",
2007 phase_map, start_final, len_final, final_phase);
2008
2009 return final_phase;
2010}
2011
2012static int

--- 136 unchanged lines hidden (view full) ---

2149}
2150
2151/*
2152 * Run the command queue.
2153 */
2154static void
2155rtsx_send_cmd(struct rtsx_softc *sc)
2156{
2074 device_printf(sc->rtsx_dev,
2075 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n",
2076 phase_map, start_final, len_final, final_phase);
2077
2078 return final_phase;
2079}
2080
2081static int

--- 136 unchanged lines hidden (view full) ---

2218}
2219
2220/*
2221 * Run the command queue.
2222 */
2223static void
2224rtsx_send_cmd(struct rtsx_softc *sc)
2225{
2157 if (bootverbose)
2226 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2158 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n");
2159
2160 sc->rtsx_intr_status = 0;
2161
2162 /* Sync command DMA buffer. */
2163 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD);
2164 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE);
2165

--- 10 unchanged lines hidden (view full) ---

2176rtsx_stop_cmd(struct rtsx_softc *sc)
2177{
2178 /* Stop command transfer. */
2179 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD);
2180
2181 /* Stop DMA transfer. */
2182 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);
2183
2227 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n");
2228
2229 sc->rtsx_intr_status = 0;
2230
2231 /* Sync command DMA buffer. */
2232 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD);
2233 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE);
2234

--- 10 unchanged lines hidden (view full) ---

2245rtsx_stop_cmd(struct rtsx_softc *sc)
2246{
2247 /* Stop command transfer. */
2248 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD);
2249
2250 /* Stop DMA transfer. */
2251 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);
2252
2253 switch (sc->rtsx_device_id) {
2254 case RTSX_RTS5260:
2255 rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0,
2256 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST,
2257 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST);
2258 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
2259 break;
2260 }
2261
2184 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST);
2185
2186 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
2187}
2188
2189/*
2190 * Clear error.
2191 */

--- 43 unchanged lines hidden (view full) ---

2235 * Send request.
2236 */
2237static int
2238rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd)
2239{
2240 uint8_t rsp_type;
2241 uint16_t reg;
2242
2262 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST);
2263
2264 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
2265}
2266
2267/*
2268 * Clear error.
2269 */

--- 43 unchanged lines hidden (view full) ---

2313 * Send request.
2314 */
2315static int
2316rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd)
2317{
2318 uint8_t rsp_type;
2319 uint16_t reg;
2320
2243 if (bootverbose)
2321 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2244 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode);
2245
2246 /* Convert response type. */
2247 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK);
2248 if (rsp_type == 0) {
2249 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK));
2250 cmd->error = MMC_ERR_INVALID;
2251 return (MMC_ERR_INVALID);

--- 64 unchanged lines hidden (view full) ---

2316 /* Sync command DMA buffer. */
2317 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD);
2318 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE);
2319
2320 /* Copy card response into mmc response buffer. */
2321 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) {
2322 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem);
2323
2322 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode);
2323
2324 /* Convert response type. */
2325 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK);
2326 if (rsp_type == 0) {
2327 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK));
2328 cmd->error = MMC_ERR_INVALID;
2329 return (MMC_ERR_INVALID);

--- 64 unchanged lines hidden (view full) ---

2394 /* Sync command DMA buffer. */
2395 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD);
2396 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE);
2397
2398 /* Copy card response into mmc response buffer. */
2399 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) {
2400 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem);
2401
2324 if (bootverbose) {
2402 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) {
2325 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
2326 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]);
2327 }
2328
2329 if (rsp_type == RTSX_SD_RSP_TYPE_R2) {
2330 /* First byte is CHECK_REG_CMD return value, skip it. */
2331 unsigned char *ptr = (unsigned char *)cmd_buffer + 1;
2332 int i;

--- 12 unchanged lines hidden (view full) ---

2345 * First byte is CHECK_REG_CMD return value, second
2346 * one is the command op code -- we skip those.
2347 */
2348 cmd->resp[0] =
2349 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) |
2350 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16);
2351 }
2352
2403 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
2404 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]);
2405 }
2406
2407 if (rsp_type == RTSX_SD_RSP_TYPE_R2) {
2408 /* First byte is CHECK_REG_CMD return value, skip it. */
2409 unsigned char *ptr = (unsigned char *)cmd_buffer + 1;
2410 int i;

--- 12 unchanged lines hidden (view full) ---

2423 * First byte is CHECK_REG_CMD return value, second
2424 * one is the command op code -- we skip those.
2425 */
2426 cmd->resp[0] =
2427 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) |
2428 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16);
2429 }
2430
2353 if (bootverbose)
2431 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2354 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n",
2355 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
2356 }
2357}
2358
2359/*
2360 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes.
2361 */

--- 6 unchanged lines hidden (view full) ---

2368 cmd->error = MMC_ERR_INVALID;
2369 return (MMC_ERR_INVALID);
2370 }
2371 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
2372 RTSX_MAX_DATA_BLKLEN : cmd->data->len;
2373
2374 read = ISSET(cmd->data->flags, MMC_DATA_READ);
2375
2432 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n",
2433 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
2434 }
2435}
2436
2437/*
2438 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes.
2439 */

--- 6 unchanged lines hidden (view full) ---

2446 cmd->error = MMC_ERR_INVALID;
2447 return (MMC_ERR_INVALID);
2448 }
2449 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
2450 RTSX_MAX_DATA_BLKLEN : cmd->data->len;
2451
2452 read = ISSET(cmd->data->flags, MMC_DATA_READ);
2453
2376 if (bootverbose)
2454 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2377 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n",
2378 read ? "Read" : "Write",
2379 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len);
2380
2381 if (cmd->data->len > 512) {
2382 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n",
2383 (unsigned long)cmd->data->len);
2384 cmd->error = MMC_ERR_INVALID;

--- 101 unchanged lines hidden (view full) ---

2486 }
2487
2488 /* Set transfer OK function. */
2489 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2;
2490
2491 /* Run the command queue. */
2492 rtsx_send_cmd(sc);
2493 } else {
2455 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n",
2456 read ? "Read" : "Write",
2457 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len);
2458
2459 if (cmd->data->len > 512) {
2460 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n",
2461 (unsigned long)cmd->data->len);
2462 cmd->error = MMC_ERR_INVALID;

--- 101 unchanged lines hidden (view full) ---

2564 }
2565
2566 /* Set transfer OK function. */
2567 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2;
2568
2569 /* Run the command queue. */
2570 rtsx_send_cmd(sc);
2571 } else {
2494 if (bootverbose && cmd->opcode == ACMD_SEND_SCR) {
2572 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) {
2495 uint8_t *ptr = cmd->data->data;
2496 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2497 ptr[0], ptr[1], ptr[2], ptr[3],
2498 ptr[4], ptr[5], ptr[6], ptr[7]);
2499 }
2500
2501 if (sc->rtsx_discovery_mode)
2502 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128);

--- 135 unchanged lines hidden (view full) ---

2638static int
2639rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd)
2640{
2641 int read = ISSET(cmd->data->flags, MMC_DATA_READ);
2642
2643 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
2644 RTSX_MAX_DATA_BLKLEN : cmd->data->len;
2645
2573 uint8_t *ptr = cmd->data->data;
2574 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2575 ptr[0], ptr[1], ptr[2], ptr[3],
2576 ptr[4], ptr[5], ptr[6], ptr[7]);
2577 }
2578
2579 if (sc->rtsx_discovery_mode)
2580 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128);

--- 135 unchanged lines hidden (view full) ---

2716static int
2717rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd)
2718{
2719 int read = ISSET(cmd->data->flags, MMC_DATA_READ);
2720
2721 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
2722 RTSX_MAX_DATA_BLKLEN : cmd->data->len;
2723
2646 if (bootverbose)
2724 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2647 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n",
2648 read ? "Read" : "Write",
2649 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len);
2650
2651 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) {
2652 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %d\n",
2653 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE);
2654 cmd->error = MMC_ERR_INVALID;

--- 19 unchanged lines hidden (view full) ---

2674 */
2675static void
2676rtsx_xfer_begin(struct rtsx_softc *sc)
2677{
2678 struct mmc_command *cmd;
2679
2680 cmd = sc->rtsx_req->cmd;
2681
2725 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n",
2726 read ? "Read" : "Write",
2727 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len);
2728
2729 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) {
2730 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %d\n",
2731 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE);
2732 cmd->error = MMC_ERR_INVALID;

--- 19 unchanged lines hidden (view full) ---

2752 */
2753static void
2754rtsx_xfer_begin(struct rtsx_softc *sc)
2755{
2756 struct mmc_command *cmd;
2757
2758 cmd = sc->rtsx_req->cmd;
2759
2682 if (bootverbose)
2760 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2683 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode);
2684
2685 rtsx_set_resp(sc, cmd);
2686 rtsx_xfer_start(sc);
2687}
2688
2689/*
2690 * Start dma data transfer.

--- 96 unchanged lines hidden (view full) ---

2787static void
2788rtsx_xfer_finish(struct rtsx_softc *sc)
2789{
2790 struct mmc_command *cmd;
2791 int read;
2792
2793 cmd = sc->rtsx_req->cmd;
2794
2761 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode);
2762
2763 rtsx_set_resp(sc, cmd);
2764 rtsx_xfer_start(sc);
2765}
2766
2767/*
2768 * Start dma data transfer.

--- 96 unchanged lines hidden (view full) ---

2865static void
2866rtsx_xfer_finish(struct rtsx_softc *sc)
2867{
2868 struct mmc_command *cmd;
2869 int read;
2870
2871 cmd = sc->rtsx_req->cmd;
2872
2795 if (bootverbose)
2873 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
2796 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode);
2797
2798 read = ISSET(cmd->data->flags, MMC_DATA_READ);
2799
2800 /* Sync data DMA buffer. */
2801 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD);
2802 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE);
2803

--- 60 unchanged lines hidden (view full) ---

2864
2865 ios = &sc->rtsx_host.ios;
2866 new_ios = &cts->ios;
2867
2868 /* Update only requested fields */
2869 if (cts->ios_valid & MMC_CLK) {
2870 ios->clock = new_ios->clock;
2871 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2874 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode);
2875
2876 read = ISSET(cmd->data->flags, MMC_DATA_READ);
2877
2878 /* Sync data DMA buffer. */
2879 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD);
2880 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE);
2881

--- 60 unchanged lines hidden (view full) ---

2942
2943 ios = &sc->rtsx_host.ios;
2944 new_ios = &cts->ios;
2945
2946 /* Update only requested fields */
2947 if (cts->ios_valid & MMC_CLK) {
2948 ios->clock = new_ios->clock;
2949 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2872 if (bootverbose || sc->rtsx_debug)
2950 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2873 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock);
2874 }
2875 if (cts->ios_valid & MMC_VDD) {
2876 ios->vdd = new_ios->vdd;
2951 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock);
2952 }
2953 if (cts->ios_valid & MMC_VDD) {
2954 ios->vdd = new_ios->vdd;
2877 if (bootverbose || sc->rtsx_debug)
2955 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2878 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd);
2879 }
2880 if (cts->ios_valid & MMC_CS) {
2881 ios->chip_select = new_ios->chip_select;
2956 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd);
2957 }
2958 if (cts->ios_valid & MMC_CS) {
2959 ios->chip_select = new_ios->chip_select;
2882 if (bootverbose || sc->rtsx_debug)
2960 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2883 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select);
2884 }
2885 if (cts->ios_valid & MMC_BW) {
2886 ios->bus_width = new_ios->bus_width;
2887 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2961 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select);
2962 }
2963 if (cts->ios_valid & MMC_BW) {
2964 ios->bus_width = new_ios->bus_width;
2965 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2888 if (bootverbose || sc->rtsx_debug)
2966 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2889 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width);
2890 }
2891 if (cts->ios_valid & MMC_PM) {
2892 ios->power_mode = new_ios->power_mode;
2893 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2967 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width);
2968 }
2969 if (cts->ios_valid & MMC_PM) {
2970 ios->power_mode = new_ios->power_mode;
2971 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2894 if (bootverbose || sc->rtsx_debug)
2972 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2895 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode);
2896 }
2897 if (cts->ios_valid & MMC_BT) {
2898 ios->timing = new_ios->timing;
2899 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2973 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode);
2974 }
2975 if (cts->ios_valid & MMC_BT) {
2976 ios->timing = new_ios->timing;
2977 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2900 if (bootverbose || sc->rtsx_debug)
2978 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2901 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing);
2902 }
2903 if (cts->ios_valid & MMC_BM) {
2904 ios->bus_mode = new_ios->bus_mode;
2979 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing);
2980 }
2981 if (cts->ios_valid & MMC_BM) {
2982 ios->bus_mode = new_ios->bus_mode;
2905 if (bootverbose || sc->rtsx_debug)
2983 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2906 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode);
2907 }
2908#if __FreeBSD_version >= 1300000
2909 if (cts->ios_valid & MMC_VCCQ) {
2910 ios->vccq = new_ios->vccq;
2911 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2984 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode);
2985 }
2986#if __FreeBSD_version >= 1300000
2987 if (cts->ios_valid & MMC_VCCQ) {
2988 ios->vccq = new_ios->vccq;
2989 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */
2912 if (bootverbose || sc->rtsx_debug)
2990 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
2913 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq);
2914 }
2915#endif /* __FreeBSD_version >= 1300000 */
2916 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0)
2917 return (CAM_REQ_CMP);
2918 else
2919 return (CAM_REQ_CMP_ERR);
2920}

--- 76 unchanged lines hidden (view full) ---

2997 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE;
2998 break;
2999 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */
3000 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */
3001 default:
3002 return (EINVAL);
3003 }
3004
2991 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq);
2992 }
2993#endif /* __FreeBSD_version >= 1300000 */
2994 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0)
2995 return (CAM_REQ_CMP);
2996 else
2997 return (CAM_REQ_CMP_ERR);
2998}

--- 76 unchanged lines hidden (view full) ---

3075 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE;
3076 break;
3077 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */
3078 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */
3079 default:
3080 return (EINVAL);
3081 }
3082
3005 if (bootverbose)
3083 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3006 device_printf(bus, "Read ivar #%d, value %#x / #%d\n",
3007 which, *(int *)result, *(int *)result);
3008
3009 return (0);
3010}
3011
3012static int
3013rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
3014{
3015 struct rtsx_softc *sc;
3016
3084 device_printf(bus, "Read ivar #%d, value %#x / #%d\n",
3085 which, *(int *)result, *(int *)result);
3086
3087 return (0);
3088}
3089
3090static int
3091rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
3092{
3093 struct rtsx_softc *sc;
3094
3017 if (bootverbose)
3095 sc = device_get_softc(bus);
3096 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3018 device_printf(bus, "Write ivar #%d, value %#x / #%d\n",
3019 which, (int)value, (int)value);
3020
3097 device_printf(bus, "Write ivar #%d, value %#x / #%d\n",
3098 which, (int)value, (int)value);
3099
3021 sc = device_get_softc(bus);
3022 switch (which) {
3023 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */
3024 sc->rtsx_host.ios.bus_mode = value;
3025 break;
3026 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */
3027 sc->rtsx_host.ios.bus_width = value;
3028 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */
3029 break;

--- 45 unchanged lines hidden (view full) ---

3075{
3076 struct rtsx_softc *sc;
3077 struct mmc_ios *ios;
3078 int error;
3079
3080 sc = device_get_softc(bus);
3081 ios = &sc->rtsx_host.ios;
3082
3100 switch (which) {
3101 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */
3102 sc->rtsx_host.ios.bus_mode = value;
3103 break;
3104 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */
3105 sc->rtsx_host.ios.bus_width = value;
3106 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */
3107 break;

--- 45 unchanged lines hidden (view full) ---

3153{
3154 struct rtsx_softc *sc;
3155 struct mmc_ios *ios;
3156 int error;
3157
3158 sc = device_get_softc(bus);
3159 ios = &sc->rtsx_host.ios;
3160
3083 if (bootverbose)
3161 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3084 device_printf(bus, "rtsx_mmcbr_update_ios()\n");
3085
3086 /* if MMCBR_IVAR_BUS_WIDTH updated. */
3087 if (sc->rtsx_ios_bus_width < 0) {
3088 sc->rtsx_ios_bus_width = ios->bus_width;
3089 if ((error = rtsx_set_bus_width(sc, ios->bus_width)))
3090 return (error);
3091 }

--- 99 unchanged lines hidden (view full) ---

3191 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val)))
3192 return (error);
3193 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE,
3194 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3)))
3195 return (error);
3196 if ((error = rtsx_rts5249_fill_driving(sc)))
3197 return (error);
3198 break;
3162 device_printf(bus, "rtsx_mmcbr_update_ios()\n");
3163
3164 /* if MMCBR_IVAR_BUS_WIDTH updated. */
3165 if (sc->rtsx_ios_bus_width < 0) {
3166 sc->rtsx_ios_bus_width = ios->bus_width;
3167 if ((error = rtsx_set_bus_width(sc, ios->bus_width)))
3168 return (error);
3169 }

--- 99 unchanged lines hidden (view full) ---

3269 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val)))
3270 return (error);
3271 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE,
3272 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3)))
3273 return (error);
3274 if ((error = rtsx_rts5249_fill_driving(sc)))
3275 return (error);
3276 break;
3277 case RTSX_RTS5260:
3278 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1);
3279 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33);
3280 if ((error = rtsx_rts5260_fill_driving(sc)))
3281 return (error);
3282 break;
3199 case RTSX_RTL8402:
3200 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
3201 RTSX_BITOP(sc, RTSX_LDO_CTL,
3202 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK,
3203 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3);
3204 break;
3205 case RTSX_RTL8411:
3206 case RTSX_RTL8411B:
3207 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
3208 RTSX_BITOP(sc, RTSX_LDO_CTL,
3209 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK,
3210 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3);
3211 break;
3212 }
3213 DELAY(300);
3214 }
3215
3283 case RTSX_RTL8402:
3284 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
3285 RTSX_BITOP(sc, RTSX_LDO_CTL,
3286 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK,
3287 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3);
3288 break;
3289 case RTSX_RTL8411:
3290 case RTSX_RTL8411B:
3291 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3);
3292 RTSX_BITOP(sc, RTSX_LDO_CTL,
3293 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK,
3294 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3);
3295 break;
3296 }
3297 DELAY(300);
3298 }
3299
3216 if (bootverbose || sc->rtsx_debug)
3300 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD))
3217 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq);
3218
3219 return (0);
3220}
3221
3222#ifndef MMCCAM
3223/*
3224 * Tune card if bus_timing_uhs_sdr50.

--- 4 unchanged lines hidden (view full) ---

3229 struct rtsx_softc *sc;
3230 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0};
3231 uint32_t phase_map;
3232 uint8_t final_phase;
3233 int i;
3234
3235 sc = device_get_softc(bus);
3236
3301 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq);
3302
3303 return (0);
3304}
3305
3306#ifndef MMCCAM
3307/*
3308 * Tune card if bus_timing_uhs_sdr50.

--- 4 unchanged lines hidden (view full) ---

3313 struct rtsx_softc *sc;
3314 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0};
3315 uint32_t phase_map;
3316 uint8_t final_phase;
3317 int i;
3318
3319 sc = device_get_softc(bus);
3320
3237 if (bootverbose || sc->rtsx_debug)
3321 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3238 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n",
3239 (hs400) ? "true" : "false");
3240
3241 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50)
3242 return (0);
3243
3244 sc->rtsx_tuning_mode = true;
3245

--- 23 unchanged lines hidden (view full) ---

3269 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) {
3270 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i]));
3271 if (raw_phase_map[i] == 0)
3272 break;
3273 }
3274
3275 phase_map = 0xffffffff;
3276 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) {
3322 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n",
3323 (hs400) ? "true" : "false");
3324
3325 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50)
3326 return (0);
3327
3328 sc->rtsx_tuning_mode = true;
3329

--- 23 unchanged lines hidden (view full) ---

3353 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) {
3354 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i]));
3355 if (raw_phase_map[i] == 0)
3356 break;
3357 }
3358
3359 phase_map = 0xffffffff;
3360 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) {
3277 if (bootverbose || sc->rtsx_debug)
3361 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING))
3278 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n",
3279 i, raw_phase_map[i]);
3280 phase_map &= raw_phase_map[i];
3281 }
3362 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n",
3363 i, raw_phase_map[i]);
3364 phase_map &= raw_phase_map[i];
3365 }
3282 if (bootverbose || sc->rtsx_debug)
3366 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3283 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map);
3284
3285 if (phase_map) {
3286 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map);
3287 if (final_phase != 0xff) {
3367 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map);
3368
3369 if (phase_map) {
3370 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map);
3371 if (final_phase != 0xff) {
3288 if (sc->rtsx_debug == 1) {
3289 sc->rtsx_debug = 2;
3290 rtsx_sd_change_rx_phase(sc, final_phase);
3291 sc->rtsx_debug = 1;
3292 } else {
3293 rtsx_sd_change_rx_phase(sc, final_phase);
3294 }
3372 rtsx_sd_change_rx_phase(sc, final_phase);
3295 }
3296 }
3297
3298 sc->rtsx_tuning_mode = false;
3299
3300 return (0);
3301}
3302
3303static int
3304rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused)
3305{
3306 struct rtsx_softc *sc;
3307
3308 sc = device_get_softc(bus);
3309
3373 }
3374 }
3375
3376 sc->rtsx_tuning_mode = false;
3377
3378 return (0);
3379}
3380
3381static int
3382rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused)
3383{
3384 struct rtsx_softc *sc;
3385
3386 sc = device_get_softc(bus);
3387
3310 if (bootverbose)
3388 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3311 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n");
3312
3313 return (0);
3314}
3315#endif /* !MMCCAM */
3316
3317static int
3318rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req)

--- 12 unchanged lines hidden (view full) ---

3331 }
3332 sc->rtsx_req = req;
3333 cmd = req->cmd;
3334 cmd->error = error = MMC_ERR_NONE;
3335 sc->rtsx_intr_status = 0;
3336 sc->rtsx_intr_trans_ok = NULL;
3337 sc->rtsx_intr_trans_ko = rtsx_req_done;
3338
3389 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n");
3390
3391 return (0);
3392}
3393#endif /* !MMCCAM */
3394
3395static int
3396rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req)

--- 12 unchanged lines hidden (view full) ---

3409 }
3410 sc->rtsx_req = req;
3411 cmd = req->cmd;
3412 cmd->error = error = MMC_ERR_NONE;
3413 sc->rtsx_intr_status = 0;
3414 sc->rtsx_intr_trans_ok = NULL;
3415 sc->rtsx_intr_trans_ko = rtsx_req_done;
3416
3339 if (bootverbose)
3417 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3340 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n",
3341 cmd->opcode, cmd->arg, cmd->flags,
3342 cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
3343 cmd->data != NULL ? cmd->data->flags : 0);
3344
3345 /* Check if card present. */
3346 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) {
3347 cmd->error = error = MMC_ERR_FAILED;

--- 53 unchanged lines hidden (view full) ---

3401 return !(sc->rtsx_read_only);
3402}
3403
3404static int
3405rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused)
3406{
3407 struct rtsx_softc *sc;
3408
3418 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n",
3419 cmd->opcode, cmd->arg, cmd->flags,
3420 cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
3421 cmd->data != NULL ? cmd->data->flags : 0);
3422
3423 /* Check if card present. */
3424 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) {
3425 cmd->error = error = MMC_ERR_FAILED;

--- 53 unchanged lines hidden (view full) ---

3479 return !(sc->rtsx_read_only);
3480}
3481
3482static int
3483rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused)
3484{
3485 struct rtsx_softc *sc;
3486
3409 if (bootverbose)
3487 sc = device_get_softc(bus);
3488 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3410 device_printf(bus, "rtsx_mmcbr_acquire_host()\n");
3411
3489 device_printf(bus, "rtsx_mmcbr_acquire_host()\n");
3490
3412 sc = device_get_softc(bus);
3413 RTSX_LOCK(sc);
3414 while (sc->rtsx_bus_busy)
3415 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0);
3416 sc->rtsx_bus_busy++;
3417 RTSX_UNLOCK(sc);
3418
3419 return (0);
3420}
3421
3422static int
3423rtsx_mmcbr_release_host(device_t bus, device_t child __unused)
3424{
3425 struct rtsx_softc *sc;
3426
3491 RTSX_LOCK(sc);
3492 while (sc->rtsx_bus_busy)
3493 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0);
3494 sc->rtsx_bus_busy++;
3495 RTSX_UNLOCK(sc);
3496
3497 return (0);
3498}
3499
3500static int
3501rtsx_mmcbr_release_host(device_t bus, device_t child __unused)
3502{
3503 struct rtsx_softc *sc;
3504
3427 if (bootverbose)
3505 sc = device_get_softc(bus);
3506 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD)
3428 device_printf(bus, "rtsx_mmcbr_release_host()\n");
3429
3507 device_printf(bus, "rtsx_mmcbr_release_host()\n");
3508
3430 sc = device_get_softc(bus);
3431 RTSX_LOCK(sc);
3432 sc->rtsx_bus_busy--;
3433 wakeup(&sc->rtsx_bus_busy);
3434 RTSX_UNLOCK(sc);
3435
3436 return (0);
3437}
3438#endif /* !MMCCAM */

--- 58 unchanged lines hidden (view full) ---

3497
3498 sc->rtsx_dev = dev;
3499 sc->rtsx_req = NULL;
3500 sc->rtsx_timeout_cmd = 1;
3501 sc->rtsx_timeout_io = 10;
3502 sc->rtsx_read_only = 0;
3503 sc->rtsx_inversion = 0;
3504 sc->rtsx_force_timing = 0;
3509 RTSX_LOCK(sc);
3510 sc->rtsx_bus_busy--;
3511 wakeup(&sc->rtsx_bus_busy);
3512 RTSX_UNLOCK(sc);
3513
3514 return (0);
3515}
3516#endif /* !MMCCAM */

--- 58 unchanged lines hidden (view full) ---

3575
3576 sc->rtsx_dev = dev;
3577 sc->rtsx_req = NULL;
3578 sc->rtsx_timeout_cmd = 1;
3579 sc->rtsx_timeout_io = 10;
3580 sc->rtsx_read_only = 0;
3581 sc->rtsx_inversion = 0;
3582 sc->rtsx_force_timing = 0;
3505 sc->rtsx_debug = 0;
3583 sc->rtsx_debug_mask = 0;
3506 sc->rtsx_read_count = 0;
3507 sc->rtsx_write_count = 0;
3508
3509 maker = kern_getenv("smbios.system.maker");
3510 family = kern_getenv("smbios.system.family");
3511 product = kern_getenv("smbios.system.product");
3512 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) {
3513 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 &&

--- 15 unchanged lines hidden (view full) ---

3529 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW,
3530 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds");
3531 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD,
3532 &sc->rtsx_read_only, 0, "Card is write protected");
3533 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN,
3534 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status");
3535 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW,
3536 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50");
3584 sc->rtsx_read_count = 0;
3585 sc->rtsx_write_count = 0;
3586
3587 maker = kern_getenv("smbios.system.maker");
3588 family = kern_getenv("smbios.system.family");
3589 product = kern_getenv("smbios.system.product");
3590 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) {
3591 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 &&

--- 15 unchanged lines hidden (view full) ---

3607 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW,
3608 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds");
3609 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD,
3610 &sc->rtsx_read_only, 0, "Card is write protected");
3611 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN,
3612 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status");
3613 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW,
3614 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50");
3537 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug", CTLFLAG_RWTUN,
3538 &sc->rtsx_debug, 0, "Debugging flag");
3615 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug_mask", CTLFLAG_RWTUN,
3616 &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)");
3539 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS,
3540 &sc->rtsx_read_count, 0, "Count of read operations");
3541 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS,
3542 &sc->rtsx_write_count, 0, "Count of write operations");
3543
3617 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS,
3618 &sc->rtsx_read_count, 0, "Count of read operations");
3619 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS,
3620 &sc->rtsx_write_count, 0, "Count of write operations");
3621
3544 if (bootverbose || sc->rtsx_debug)
3622 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC)
3545 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion);
3546
3547 /* Allocate IRQ. */
3548 sc->rtsx_irq_res_id = 0;
3549 if (pci_alloc_msi(dev, &msi_count) == 0)
3550 sc->rtsx_irq_res_id = 1;
3551 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id,
3552 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE));

--- 241 unchanged lines hidden --- 		3623 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion);
3624
3625 /* Allocate IRQ. */
3626 sc->rtsx_irq_res_id = 0;
3627 if (pci_alloc_msi(dev, &msi_count) == 0)
3628 sc->rtsx_irq_res_id = 1;
3629 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id,
3630 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE));

--- 241 unchanged lines hidden ---