ioat_internal.h (5f77bd3e244b85b4bbd5ab7386e7d5fbf4fe4316) ioat_internal.h (faefad9c125a9478dd46ccadd0b20a2c825de803)
1/*-
2 * Copyright (C) 2012 Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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338 struct ioat_fill_hw_descriptor *fill;
339 struct ioat_xor_hw_descriptor *xor;
340 struct ioat_xor_ext_hw_descriptor *xor_ext;
341 struct ioat_pq_hw_descriptor *pq;
342 struct ioat_pq_ext_hw_descriptor *pq_ext;
343 struct ioat_raw_hw_descriptor *raw;
344 } u;
345 uint32_t id;
1/*-
2 * Copyright (C) 2012 Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 329 unchanged lines hidden (view full) ---

338 struct ioat_fill_hw_descriptor *fill;
339 struct ioat_xor_hw_descriptor *xor;
340 struct ioat_xor_ext_hw_descriptor *xor_ext;
341 struct ioat_pq_hw_descriptor *pq;
342 struct ioat_pq_ext_hw_descriptor *pq_ext;
343 struct ioat_raw_hw_descriptor *raw;
344 } u;
345 uint32_t id;
346 uint32_t length;
347 enum validate_flags *validate_result;
348 bus_addr_t hw_desc_bus_addr;
349};
350
351enum ioat_ref_kind {
352 IOAT_DMAENGINE_REF = 0,
353 IOAT_ACTIVE_DESCR_REF,
354 IOAT_NUM_REF_KINDS
355};

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346 bus_addr_t hw_desc_bus_addr;
347};
348
349enum ioat_ref_kind {
350 IOAT_DMAENGINE_REF = 0,
351 IOAT_ACTIVE_DESCR_REF,
352 IOAT_NUM_REF_KINDS
353};

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