| ioat_hw.h (11d38a5764295585a2472d5e861fa8abe1a11eb2) | ioat_hw.h (faefad9c125a9478dd46ccadd0b20a2c825de803) |
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| 1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 67 unchanged lines hidden (view full) --- 76#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 77#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 78#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 79#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 80#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 81#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 82#define IOAT_CHANCTRL_INT_REARM 0x0001 83#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ | 1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 67 unchanged lines hidden (view full) --- 76#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200 77#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 78#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 79#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 80#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 81#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 82#define IOAT_CHANCTRL_INT_REARM 0x0001 83#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ |
| 84 IOAT_CHANCTRL_ANY_ERR_ABORT_EN) | 84 IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 85 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\ 86 IOAT_CHANCTRL_ERR_INT_EN) |
| 85 86#define IOAT_CHANCMD_OFFSET 0x84 87#define IOAT_CHANCMD_RESET 0x20 88#define IOAT_CHANCMD_SUSPEND 0x04 89 90#define IOAT_DMACOUNT_OFFSET 0x86 91 92#define IOAT_CHANSTS_OFFSET_LOW 0x88 93#define IOAT_CHANSTS_OFFSET_HIGH 0x8C 94#define IOAT_CHANSTS_OFFSET 0x88 95 96#define IOAT_CHANSTS_STATUS 0x7ULL 97#define IOAT_CHANSTS_ACTIVE 0x0 98#define IOAT_CHANSTS_IDLE 0x1 99#define IOAT_CHANSTS_SUSPENDED 0x2 100#define IOAT_CHANSTS_HALTED 0x3 | 87 88#define IOAT_CHANCMD_OFFSET 0x84 89#define IOAT_CHANCMD_RESET 0x20 90#define IOAT_CHANCMD_SUSPEND 0x04 91 92#define IOAT_DMACOUNT_OFFSET 0x86 93 94#define IOAT_CHANSTS_OFFSET_LOW 0x88 95#define IOAT_CHANSTS_OFFSET_HIGH 0x8C 96#define IOAT_CHANSTS_OFFSET 0x88 97 98#define IOAT_CHANSTS_STATUS 0x7ULL 99#define IOAT_CHANSTS_ACTIVE 0x0 100#define IOAT_CHANSTS_IDLE 0x1 101#define IOAT_CHANSTS_SUSPENDED 0x2 102#define IOAT_CHANSTS_HALTED 0x3 |
| 103#define IOAT_CHANSTS_ARMED 0x4 |
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| 101 102#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL 103#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL 104 105#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) 106 107#define IOAT_CHAINADDR_OFFSET_LOW 0x90 108#define IOAT_CHAINADDR_OFFSET_HIGH 0x94 --- 49 unchanged lines hidden --- | 104 105#define IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL 106#define IOAT_CHANSTS_SOFT_ERROR 0x10ULL 107 108#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL) 109 110#define IOAT_CHAINADDR_OFFSET_LOW 0x90 111#define IOAT_CHAINADDR_OFFSET_HIGH 0x94 --- 49 unchanged lines hidden --- |