| fwohci.c (9950b741e91ab7a7e26badccc0d82f2e103a1f1e) | fwohci.c (ac2d2894b48d170a998e294c0fc8df0bbd783705) |
|---|---|
| 1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 65 unchanged lines hidden (view full) --- 74#include <dev/firewire/fwohcireg.h> 75#include <dev/firewire/fwohcivar.h> 76#include <dev/firewire/firewire_phy.h> 77#endif 78 79#undef OHCI_DEBUG 80 81static int nocyclemaster = 0; | 1/*- 2 * Copyright (c) 2003 Hidetoshi Shimokawa 3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 65 unchanged lines hidden (view full) --- 74#include <dev/firewire/fwohcireg.h> 75#include <dev/firewire/fwohcivar.h> 76#include <dev/firewire/firewire_phy.h> 77#endif 78 79#undef OHCI_DEBUG 80 81static int nocyclemaster = 0; |
| 82int firewire_phydma_enable = 1; |
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| 82SYSCTL_DECL(_hw_firewire); 83SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 84 "Do not send cycle start packets"); | 83SYSCTL_DECL(_hw_firewire); 84SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0, 85 "Do not send cycle start packets"); |
| 86SYSCTL_INT(_hw_firewire, OID_AUTO, phydma_enable, CTLFLAG_RW, 87 &firewire_phydma_enable, 1, "Allow physical request DMA from firewire"); 88TUNABLE_INT("hw.firewire.phydma_enable", &firewire_phydma_enable); |
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| 85 86static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 87 "STOR","LOAD","NOP ","STOP",}; 88 89static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 90 "UNDEF","REG","SYS","DEV"}; 91static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 92char fwohcicode[32][0x20]={ --- 1764 unchanged lines hidden (view full) --- 1857 } 1858 if (stat & OHCI_INT_PHY_SID) { 1859 /* Enable bus reset interrupt */ 1860 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1861 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1862 1863 /* Allow async. request to us */ 1864 OWRITE(sc, OHCI_AREQHI, 1 << 31); | 89 90static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 91 "STOR","LOAD","NOP ","STOP",}; 92 93static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 94 "UNDEF","REG","SYS","DEV"}; 95static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 96char fwohcicode[32][0x20]={ --- 1764 unchanged lines hidden (view full) --- 1861 } 1862 if (stat & OHCI_INT_PHY_SID) { 1863 /* Enable bus reset interrupt */ 1864 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1865 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); 1866 1867 /* Allow async. request to us */ 1868 OWRITE(sc, OHCI_AREQHI, 1 << 31); |
| 1865 /* XXX insecure ?? */ 1866 /* allow from all nodes */ 1867 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1868 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1869 /* 0 to 4GB regison */ 1870 OWRITE(sc, OHCI_PREQUPPER, 0x10000); | 1869 if (firewire_phydma_enable) { 1870 /* allow from all nodes */ 1871 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1872 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1873 /* 0 to 4GB region */ 1874 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1875 } |
| 1871 /* Set ATRetries register */ 1872 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1873 1874 /* 1875 * Checking whether the node is root or not. If root, turn on 1876 * cycle master. 1877 */ 1878 node_id = OREAD(sc, FWOHCI_NODEID); --- 1095 unchanged lines hidden --- | 1876 /* Set ATRetries register */ 1877 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); 1878 1879 /* 1880 * Checking whether the node is root or not. If root, turn on 1881 * cycle master. 1882 */ 1883 node_id = OREAD(sc, FWOHCI_NODEID); --- 1095 unchanged lines hidden --- |