ata-nvidia.c (874108aed99d76099ff9eb6c8d830479a504c1ad) ata-nvidia.c (066f913a94b134b6d5e32b6af88f297c7da9c031)
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_nvidia_chipinit(device_t dev);
56static int ata_nvidia_ch_attach(device_t dev);
57static int ata_nvidia_status(device_t dev);
58static void ata_nvidia_reset(device_t dev);
1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_nvidia_chipinit(device_t dev);
56static int ata_nvidia_ch_attach(device_t dev);
57static int ata_nvidia_status(device_t dev);
58static void ata_nvidia_reset(device_t dev);
59static void ata_nvidia_setmode(device_t dev, int mode);
59static int ata_nvidia_setmode(device_t dev, int target, int mode);
60
61/* misc defines */
62#define NV4 0x01
63#define NVQ 0x02
64#define NVAHCI 0x04
65
66
67/*

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226 /* clear interrupt status */
227 ATA_OUTB(ctlr->r_res2, offset, 0xff);
228
229 /* enable device and PHY state change interrupts */
230 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
231 }
232 }
233 ctlr->setmode = ata_sata_setmode;
60
61/* misc defines */
62#define NV4 0x01
63#define NVQ 0x02
64#define NVAHCI 0x04
65
66
67/*

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226 /* clear interrupt status */
227 ATA_OUTB(ctlr->r_res2, offset, 0xff);
228
229 /* enable device and PHY state change interrupts */
230 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
231 }
232 }
233 ctlr->setmode = ata_sata_setmode;
234 ctlr->getrev = ata_sata_getrev;
234 }
235 else {
236 /* disable prefetch, postwrite */
237 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
238 ctlr->setmode = ata_nvidia_setmode;
239 }
240 return 0;
241}

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254 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
255 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
256 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
257 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
258 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
259
260 ch->hw.status = ata_nvidia_status;
261 ch->flags |= ATA_NO_SLAVE;
235 }
236 else {
237 /* disable prefetch, postwrite */
238 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
239 ctlr->setmode = ata_nvidia_setmode;
240 }
241 return 0;
242}

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255 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
256 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
257 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
258 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
259 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
260
261 ch->hw.status = ata_nvidia_status;
262 ch->flags |= ATA_NO_SLAVE;
262
263 ch->flags |= ATA_SATA;
263 return 0;
264}
265
266static int
267ata_nvidia_status(device_t dev)
268{
269 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
270 struct ata_channel *ch = device_get_softc(dev);

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294
295static void
296ata_nvidia_reset(device_t dev)
297{
298 if (ata_sata_phy_reset(dev, -1, 1))
299 ata_generic_reset(dev);
300}
301
264 return 0;
265}
266
267static int
268ata_nvidia_status(device_t dev)
269{
270 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
271 struct ata_channel *ch = device_get_softc(dev);

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295
296static void
297ata_nvidia_reset(device_t dev)
298{
299 if (ata_sata_phy_reset(dev, -1, 1))
300 ata_generic_reset(dev);
301}
302
302static void
303ata_nvidia_setmode(device_t dev, int mode)
303static int
304ata_nvidia_setmode(device_t dev, int target, int mode)
304{
305{
305 device_t gparent = GRANDPARENT(dev);
306 struct ata_pci_controller *ctlr = device_get_softc(gparent);
307 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
308 struct ata_device *atadev = device_get_softc(dev);
309 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
310 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
311 int modes[7] = { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 };
312 int devno = (ch->unit << 1) + atadev->unit;
313 int reg = 0x63 - devno;
314 int error;
306 device_t parent = device_get_parent(dev);
307 struct ata_pci_controller *ctlr = device_get_softc(parent);
308 struct ata_channel *ch = device_get_softc(dev);
309 int devno = (ch->unit << 1) + target;
310 int piomode;
311 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 };
312 int modes[7] = { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 };
313 int reg = 0x63 - devno;
315
314
316 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
317 mode = ata_check_80pin(dev, mode);
315 mode = min(mode, ctlr->chip->max_dma);
318
316
319 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
320 if (bootverbose)
321 device_printf(dev, "%ssetting %s on %s chip\n",
322 (error) ? "FAILURE " : "", ata_mode2str(mode),
323 ctlr->chip->text);
324 if (!error) {
325 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
326 if (mode >= ATA_UDMA0)
327 pci_write_config(gparent, reg, modes[mode & ATA_MODE_MASK], 1);
328 else
329 pci_write_config(gparent, reg, 0x8b, 1);
330 atadev->mode = mode;
331 }
317 if (mode >= ATA_UDMA0) {
318 pci_write_config(parent, reg, modes[mode & ATA_MODE_MASK], 1);
319 piomode = ATA_PIO4;
320 } else {
321 pci_write_config(parent, reg, 0x8b, 1);
322 piomode = mode;
323 }
324 pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(piomode)], 1);
325 return (mode);
332}
333
334ATA_DECLARE_DRIVER(ata_nvidia);
335MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1);
326}
327
328ATA_DECLARE_DRIVER(ata_nvidia);
329MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1);