ti_gpio.h (d60840138f6292c1ceeb177ebe797eca0b2749da) ti_gpio.h (59c3cb81c1769fdb6c840c971df129b52f4a848d)
1/*-
2 * Copyright (c) 2011
3 * Ben Gray <ben.r.gray@gmail.com>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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34#define MAX_GPIO_BANKS 6
35
36/*
37 * Maximum GPIOS possible, max of *_MAX_GPIO_BANKS * *_INTR_PER_BANK.
38 * These are defined in ti_gpio.c
39 */
40#define MAX_GPIO_INTRS 8
41
1/*-
2 * Copyright (c) 2011
3 * Ben Gray <ben.r.gray@gmail.com>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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34#define MAX_GPIO_BANKS 6
35
36/*
37 * Maximum GPIOS possible, max of *_MAX_GPIO_BANKS * *_INTR_PER_BANK.
38 * These are defined in ti_gpio.c
39 */
40#define MAX_GPIO_INTRS 8
41
42#ifndef ARM_INTRNG
42#ifndef INTRNG
43struct ti_gpio_mask_arg {
44 void *softc;
45 int pin;
46};
47#else
48struct ti_gpio_irqsrc {
49 struct intr_irqsrc tgi_isrc;
50 u_int tgi_irq;

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56/**
57 * Structure that stores the driver context.
58 *
59 * This structure is allocated during driver attach.
60 */
61struct ti_gpio_softc {
62 device_t sc_dev;
63 device_t sc_busdev;
43struct ti_gpio_mask_arg {
44 void *softc;
45 int pin;
46};
47#else
48struct ti_gpio_irqsrc {
49 struct intr_irqsrc tgi_isrc;
50 u_int tgi_irq;

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56/**
57 * Structure that stores the driver context.
58 *
59 * This structure is allocated during driver attach.
60 */
61struct ti_gpio_softc {
62 device_t sc_dev;
63 device_t sc_busdev;
64#ifndef ARM_INTRNG
64#ifndef INTRNG
65 /* Interrupt trigger type and level. */
66 enum intr_trigger *sc_irq_trigger;
67 enum intr_polarity *sc_irq_polarity;
68#endif
69 int sc_bank;
70 int sc_maxpin;
71 struct mtx sc_mtx;
72
73 int sc_mem_rid;
74 struct resource *sc_mem_res;
75 int sc_irq_rid;
76 struct resource *sc_irq_res;
65 /* Interrupt trigger type and level. */
66 enum intr_trigger *sc_irq_trigger;
67 enum intr_polarity *sc_irq_polarity;
68#endif
69 int sc_bank;
70 int sc_maxpin;
71 struct mtx sc_mtx;
72
73 int sc_mem_rid;
74 struct resource *sc_mem_res;
75 int sc_irq_rid;
76 struct resource *sc_irq_res;
77#ifndef ARM_INTRNG
77#ifndef INTRNG
78 /* Interrupt events. */
79 struct intr_event **sc_events;
80 struct ti_gpio_mask_arg *sc_mask_args;
81#else
82 struct ti_gpio_irqsrc *sc_isrcs;
83#endif
84 /* The handle for the register IRQ handlers. */
85 void *sc_irq_hdl;
86};
87
88#endif /* TI_GPIO_H */
78 /* Interrupt events. */
79 struct intr_event **sc_events;
80 struct ti_gpio_mask_arg *sc_mask_args;
81#else
82 struct ti_gpio_irqsrc *sc_isrcs;
83#endif
84 /* The handle for the register IRQ handlers. */
85 void *sc_irq_hdl;
86};
87
88#endif /* TI_GPIO_H */