aintc.c (2263fb580e50256fbdbb081ca0756389d72b6bfc) aintc.c (59c3cb81c1769fdb6c840c971df129b52f4a848d)
1/*-
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Based on OMAP3 INTC code by Ben Gray
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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43#include <machine/bus.h>
44#include <machine/intr.h>
45
46#include <dev/fdt/fdt_common.h>
47#include <dev/ofw/openfirm.h>
48#include <dev/ofw/ofw_bus.h>
49#include <dev/ofw/ofw_bus_subr.h>
50
1/*-
2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3 * All rights reserved.
4 *
5 * Based on OMAP3 INTC code by Ben Gray
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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43#include <machine/bus.h>
44#include <machine/intr.h>
45
46#include <dev/fdt/fdt_common.h>
47#include <dev/ofw/openfirm.h>
48#include <dev/ofw/ofw_bus.h>
49#include <dev/ofw/ofw_bus_subr.h>
50
51#ifdef ARM_INTRNG
51#ifdef INTRNG
52#include "pic_if.h"
53#endif
54
55#define INTC_REVISION 0x00
56#define INTC_SYSCONFIG 0x10
57#define INTC_SYSSTATUS 0x14
58#define INTC_SIR_IRQ 0x40
59#define INTC_CONTROL 0x48
60#define INTC_THRESHOLD 0x68
61#define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20))
62#define INTC_MIR_SET(x) (0x8C + ((x) * 0x20))
63#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20))
64#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20))
65
66#define INTC_SIR_SPURIOUS_MASK 0xffffff80
67#define INTC_SIR_ACTIVE_MASK 0x7f
68
69#define INTC_NIRQS 128
70
52#include "pic_if.h"
53#endif
54
55#define INTC_REVISION 0x00
56#define INTC_SYSCONFIG 0x10
57#define INTC_SYSSTATUS 0x14
58#define INTC_SIR_IRQ 0x40
59#define INTC_CONTROL 0x48
60#define INTC_THRESHOLD 0x68
61#define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20))
62#define INTC_MIR_SET(x) (0x8C + ((x) * 0x20))
63#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20))
64#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20))
65
66#define INTC_SIR_SPURIOUS_MASK 0xffffff80
67#define INTC_SIR_ACTIVE_MASK 0x7f
68
69#define INTC_NIRQS 128
70
71#ifdef ARM_INTRNG
71#ifdef INTRNG
72struct ti_aintc_irqsrc {
73 struct intr_irqsrc tai_isrc;
74 u_int tai_irq;
75};
76#endif
77
78struct ti_aintc_softc {
79 device_t sc_dev;
80 struct resource * aintc_res[3];
81 bus_space_tag_t aintc_bst;
82 bus_space_handle_t aintc_bsh;
83 uint8_t ver;
72struct ti_aintc_irqsrc {
73 struct intr_irqsrc tai_isrc;
74 u_int tai_irq;
75};
76#endif
77
78struct ti_aintc_softc {
79 device_t sc_dev;
80 struct resource * aintc_res[3];
81 bus_space_tag_t aintc_bst;
82 bus_space_handle_t aintc_bsh;
83 uint8_t ver;
84#ifdef ARM_INTRNG
84#ifdef INTRNG
85 struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS];
86#endif
87};
88
89static struct resource_spec ti_aintc_spec[] = {
90 { SYS_RES_MEMORY, 0, RF_ACTIVE },
91 { -1, 0 }
92};

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100
101/* List of compatible strings for FDT tree */
102static struct ofw_compat_data compat_data[] = {
103 {"ti,am33xx-intc", 1},
104 {"ti,omap2-intc", 1},
105 {NULL, 0},
106};
107
85 struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS];
86#endif
87};
88
89static struct resource_spec ti_aintc_spec[] = {
90 { SYS_RES_MEMORY, 0, RF_ACTIVE },
91 { -1, 0 }
92};

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100
101/* List of compatible strings for FDT tree */
102static struct ofw_compat_data compat_data[] = {
103 {"ti,am33xx-intc", 1},
104 {"ti,omap2-intc", 1},
105 {NULL, 0},
106};
107
108#ifdef ARM_INTRNG
108#ifdef INTRNG
109static inline void
110ti_aintc_irq_eoi(struct ti_aintc_softc *sc)
111{
112
113 aintc_write_4(sc, INTC_CONTROL, 1);
114}
115
116static inline void

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290 aintc_write_4(sc, INTC_SYSCONFIG, 2);
291
292 /* Wait for reset to complete */
293 while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1));
294
295 /*Set Priority Threshold */
296 aintc_write_4(sc, INTC_THRESHOLD, 0xFF);
297
109static inline void
110ti_aintc_irq_eoi(struct ti_aintc_softc *sc)
111{
112
113 aintc_write_4(sc, INTC_CONTROL, 1);
114}
115
116static inline void

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290 aintc_write_4(sc, INTC_SYSCONFIG, 2);
291
292 /* Wait for reset to complete */
293 while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1));
294
295 /*Set Priority Threshold */
296 aintc_write_4(sc, INTC_THRESHOLD, 0xFF);
297
298#ifndef ARM_INTRNG
298#ifndef INTRNG
299 arm_post_filter = aintc_post_filter;
300#else
301 if (ti_aintc_pic_attach(sc) != 0) {
302 device_printf(dev, "could not attach PIC\n");
303 return (ENXIO);
304 }
305#endif
306 return (0);
307}
308
309static device_method_t ti_aintc_methods[] = {
310 DEVMETHOD(device_probe, ti_aintc_probe),
311 DEVMETHOD(device_attach, ti_aintc_attach),
312
299 arm_post_filter = aintc_post_filter;
300#else
301 if (ti_aintc_pic_attach(sc) != 0) {
302 device_printf(dev, "could not attach PIC\n");
303 return (ENXIO);
304 }
305#endif
306 return (0);
307}
308
309static device_method_t ti_aintc_methods[] = {
310 DEVMETHOD(device_probe, ti_aintc_probe),
311 DEVMETHOD(device_attach, ti_aintc_attach),
312
313#ifdef ARM_INTRNG
313#ifdef INTRNG
314 DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr),
315 DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr),
316 DEVMETHOD(pic_map_intr, ti_aintc_map_intr),
317 DEVMETHOD(pic_post_filter, ti_aintc_post_filter),
318 DEVMETHOD(pic_post_ithread, ti_aintc_post_ithread),
319 DEVMETHOD(pic_pre_ithread, ti_aintc_pre_ithread),
320#endif
321

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329};
330
331static devclass_t ti_aintc_devclass;
332
333EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass,
334 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
335SIMPLEBUS_PNP_INFO(compat_data);
336
314 DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr),
315 DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr),
316 DEVMETHOD(pic_map_intr, ti_aintc_map_intr),
317 DEVMETHOD(pic_post_filter, ti_aintc_post_filter),
318 DEVMETHOD(pic_post_ithread, ti_aintc_post_ithread),
319 DEVMETHOD(pic_pre_ithread, ti_aintc_pre_ithread),
320#endif
321

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329};
330
331static devclass_t ti_aintc_devclass;
332
333EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass,
334 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
335SIMPLEBUS_PNP_INFO(compat_data);
336
337#ifndef ARM_INTRNG
337#ifndef INTRNG
338int
339arm_get_next_irq(int last_irq)
340{
341 struct ti_aintc_softc *sc = ti_aintc_sc;
342 uint32_t active_irq;
343
344 /* Get the next active interrupt */
345 active_irq = aintc_read_4(sc, INTC_SIR_IRQ);

--- 33 unchanged lines hidden --- 		338int
339arm_get_next_irq(int last_irq)
340{
341 struct ti_aintc_softc *sc = ti_aintc_sc;
342 uint32_t active_irq;
343
344 /* Get the next active interrupt */
345 active_irq = aintc_read_4(sc, INTC_SIR_IRQ);

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